Heating of Metal lines

[Yogi_bhandari]

Hello all,

Of late I have been trying to work my way back from what I am seeing in simulation. I have a suspect in my mind but am not sure how to go about it.

I suspect the metal lines used for routing will get heated up when current passes through them and besides presenting parasitic anyway will change the parasitic resistance due to the said self heating phenomenon.
Now I know the temperature change of the metal lines will be directly proportional to the square of the current density through the metal line. But am not sure what the heating coefficient should be. I am assuming the metal lines will be Aluminimum. Can anyone help?

 

[dick_freebird]

It's more complicated than that, but you're basically right.

There is a foot-race between I^2*R heating, and thermal
conduction through the oxide and metal stack to the
silicon below, and eventually the package and the
outside world. At "legal" current stresses, the temp rise
ought to be modest. In digital CMOS, aside from output
lines there is no DC current and you'd have to be pretty
high frequency for the gate displacement currents to
amount to anything thermally. Analog CMOS drivers and
power management, this could be a thing (but there I'd
expect you to be chasing on resistance so hard, that
thermal rise would be pretty low).

The temp rise is a thermal spreading phenomenon,
if it's all about one line and not a sea of uniformly
spaced, uniformly stressed lines. I have not found many
good references for thermal spreading calculation. A
thermal simulator might be better if you have process
construction details.