nanostallmann
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Hi all,
I have some questions about the timing control of signals hsync & vsync in an hdmi-tx.
I read an old post about the use of these signals but nothing about their duration or "duty-cycle" therefore I write this thread.
How sayed in other thread, the hsync is the signal for tell to reciever the extention and position of the image on the screen in horizontal direction, vsync have the same function of hsync but regarding vertical direction. The duration and "duty-cycle" of these signal depend from resolution choisen.
I understood that the signal are asserted low when the active image is transmitted, and hi when the blanking period is transmitted, but nothing about their front and back porch.
The first question is the hsync is cycled for each line of active screen area and the vsync one time after that all row are transmitted? therefore ie for VGA the signals are asserted and de-asserded 600 times hsync and 1 time vsync?
The second question is I must alternate pixel data (active period) with control (control period) for each pixel? or only for each row? therefore for VGA example I must send 600 active periods and 600 control periods?
The third question is about the duration of Ton and Toff of hsync and vsync respect the resolution choisen and the size of the monitor and blanking area. and then how can I establish their shape respect the size of monitor and active area (front and back porch)?
- Note for VGA example: refresh rate is 60 Hz then 16.7ms, with 25MHz pixel clock the pixel period is 40 ns then for 600x480 VGA resolution the time for a complete the active screen portion is 12.288ms.
Thank you very much
I have some questions about the timing control of signals hsync & vsync in an hdmi-tx.
I read an old post about the use of these signals but nothing about their duration or "duty-cycle" therefore I write this thread.
How sayed in other thread, the hsync is the signal for tell to reciever the extention and position of the image on the screen in horizontal direction, vsync have the same function of hsync but regarding vertical direction. The duration and "duty-cycle" of these signal depend from resolution choisen.
I understood that the signal are asserted low when the active image is transmitted, and hi when the blanking period is transmitted, but nothing about their front and back porch.
The first question is the hsync is cycled for each line of active screen area and the vsync one time after that all row are transmitted? therefore ie for VGA the signals are asserted and de-asserded 600 times hsync and 1 time vsync?
The second question is I must alternate pixel data (active period) with control (control period) for each pixel? or only for each row? therefore for VGA example I must send 600 active periods and 600 control periods?
The third question is about the duration of Ton and Toff of hsync and vsync respect the resolution choisen and the size of the monitor and blanking area. and then how can I establish their shape respect the size of monitor and active area (front and back porch)?
- Note for VGA example: refresh rate is 60 Hz then 16.7ms, with 25MHz pixel clock the pixel period is 40 ns then for 600x480 VGA resolution the time for a complete the active screen portion is 12.288ms.
Thank you very much
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