mrnakhkash
Newbie level 1
Hi all,
I'm giving a 2d array to a VHDL module.This 2d array is valued in a verilog module. The error that ISE is giving is that the 2d array is assumed a memory and can not be accessed. I've googled the error but there were no answers to this specific case. Please help me on this.
Here's the definition of the 2d array.
Here's the part of my verilog code that is the source of the error.
And here is the error message
I'm giving a 2d array to a VHDL module.This 2d array is valued in a verilog module. The error that ISE is giving is that the 2d array is assumed a memory and can not be accessed. I've googled the error but there were no answers to this specific case. Please help me on this.
Here's the definition of the 2d array.
Code:
wire [IN_FIFO_DEPTH_BIT:0] depth_of_fifo[NUM_QUEUES-1:0];//storing the depth of all FIFOs
wire [IN_FIFO_DEPTH_BIT - 1:0] packet_size_temp[NUM_QUEUES-1:0];Here's the part of my verilog code that is the source of the error.
Code:
Deficit_Round_Robbin_algorithem
#(
.Quantom(),
.Num_queues(NUM_QUEUES),
.IN_FIFO_DEPTH_BIT(IN_FIFO_DEPTH_BIT)
)
algorithem_module(
.clk(axi_aclk),
.axi_resetn(axi_resetn),
.m_axis_tready(m_axis_tready),
.packet_size(packet_size_temp), //Line 247
.fifo_out_tlast(fifo_out_tlast),
.empty(empty),
.rd_en(rd_en),
.pkt_fwd(pkt_fwd)
);And here is the error message
Code:
ERROR:HDLCompiler:251 - "K:/final project/codes/v3/input_arbiter.v" Line 247: Cannot access memory packet_size_temp directly
ERROR:HDLCompiler:598 - "K:/final project/codes/v3/input_arbiter.v" Line 46: Module <input_arbiter> ignored due to previous errors.