Hello everyone,
...
I can't seem to easily switch to HDL mindset.
I mean, every HDL project I try to code, I end up being intensively criticized for how ugly my HDL code design is, and it's almost a software rather than an HDL.
Much Regards
Verilog is a lower level language and should help you to go away from "software mentality", even because some higher-level concepts (floating point for example) simply does not exists here.
VHDL, for other side, being a higher level language, has a lot of temptations from a guy that has a "software mentality" - although I am sure that many will say that the important is not the language and bla bla bla.
Sorry, what? Both languages can be used for RTL description, which is what you should use to describe digital logic. Verilog and VHDL have the exact same capability to describe hardware in RTL, your argument makes no sense.
Which HDL do you use?
Verilog is a lower level language and should help you to go away from "software mentality", even because some higher-level concepts (floating point for example) simply does not exists here.
VHDL, for other side, being a higher level language, has a lot of temptations from a guy that has a "software mentality" - although I am sure that many will say that the important is not the language and bla bla bla.
What are the most common design issues your colleagues point out?
Sorry, what? Both languages can be used for RTL description, which is what you should use to describe digital logic. Verilog and VHDL have the exact same capability to describe hardware in RTL, your argument makes no sense.
Code VHDL - [expand] 1 2 3 4 5 6 process(clk) begin if rising_edge(clk) then -- Most code here is fair game IMO end if; end process;
It is generally accepted that VHDL can go to a higher level of abstraction than verilog.
I don't see how.
Please, let's not confuse the OP even more. This is not about the verification features of a language, I am talking strictly about the ability to describe hardware in RTL fashion. VHDL and verilog are equivalent. Sure, verilog allows to model transistor level delays and strength. No one uses that for actual design.
VHDL has libraries, packages, method overloading that Verilog does not. But the higher level of abstraction is mostly for simulation purposes for Modelling and when it comes to synthesisable RTL, then they are equivalent.
Sorry, what? Both languages can be used for RTL description, which is what you should use to describe digital logic. Verilog and VHDL have the exact same capability to describe hardware in RTL, your argument makes no sense.
Those are useful features at best, but they don't raise the abstraction level.No, Verilog has way less capabilities.
Thanks everyone for taking the time to reply.
Unfortunately, the little debate above of VHDL vs Verilog (and others) did confuse me a bit. I wasn't asking which is better or easier, I was asking about how not to embed all my design into one always block sequentially (which is really software coding style). Btw, my language is Verilog.
My code is synthesizable, and it did indeed work as expected when burned it into the board, but imagine having a huge cryptographical core programmed into one sequential always block, with few tasks (which I thought to use as functions in the software world), I showed that code to lots of people, almost all of them agreed that this didn't even look like a hardware code.
I'm really sorry if the question is really newbie and beginner, it's just I need to know how can I optimize my coding in order to look (and run) more like hardware style.
And are limited in the amount of logic they produce, with comments related to the maximum depth of logic that will be produced for a given set of inputs, so anyone using it later (if it can be reused) doesn't run into timing issues due to 35 levels of logic at 300 MHz (not going to happen).IMO, tasks should only be used if they are wrapping up code that is used in more than one place - because this will allow a single edit and 2+ mods (ie, where its called). If its used only once - dont use a task.
One big always block does sound software-ish.
I tent to start by thinking about functions that are needed (counter, shift register, multiplier etc) and by thinking about those functions as their own always block. If coordination is needed that warrants a central state machine that “pulls the strings” of the dumb functional blocks like a puppet master with well named control signals like “shift_en”, “shift_rst” etc.
The point is that if you have a multiply anywhere your code will synthesize a multiplier. An HDL designer will tend to write code which emphasizes that and can be more easily skimmed to inventory the hardware it’s actually creating and the signal flow between those hardware blocks.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 /* PIPELINE 1 */ always @(posedge CLK) begin (...) end /* PIPELINE 2*/ always @(posedge CLK) begin (...) end
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