HDL source code encoding-decoding

[kalex]

Hi, all,
I'd like ask this question. Does it possible (and "How to" if yes) to encode
VHDL source code of critical parts (like IPes library) of any project, while all project will still be available for normal compilation, simulation and
synthesis (by @ldec, Modelsim, LS, Synplify, etc). Maybe, like
@ltera megacores method? Anything else?
Thank in advance. :?:

 

[adanshen]

it seems that there is no the kind of common format temporary storage form,
as the gds

 

[steshenko]

IMHO it is not possible, because altera method use feature of altera tools. May be you need write a little utilities to encode/decode your sourse befor compilation or use only netlist for your core (use preroute core)