Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis.
Industry follows the similar flow : Design --> Simulation --> Synthesis --> Backend flow
Modelsim is from Mentor. Latest Modelsim version is Questa Sim which can be used to simulate System Verilog codes.
Xilinx ISE is targeted for FPGA realization. Move on to synthesis only if you are 100% sure that your design is functionally correct.
DTN