User sees everything happening once but all the processes in background runs one by one. This done with the help of
Scheduling (computing). Designing a simulator is very complex task involving hundreds of engineers and result of research of many years.
Preceding the actual simulation are two major steps (for VHDL): Ref: A VHDL primer by Bhasker
1. Elaboration phase: In this phase, the hierarchy of the entity is expanded and linked, components are bound to entities in a library and the top-level entity is built as a network of behavioral models that is ready to be simulated. Also, storage is allocated for all data objects (signals, variables, and constants) declared in the design units. Initial values are also assigned to these objects.
2. Initialization phase: The effective values for all explicitly declared signals are computed, implicit signals (discussed in later chapters) are assigned values, processes are executed once until they suspend, and simulation time is reset to 0 ns.
Simulation commences by advancing time to that of the next event. Values that are scheduled to be assigned to signals at this time are assigned. Each process that has a signal in its sensitivity list whose value just changed, is executed until it suspends. Simulation stops when a user-specified time limit is reached, or when an assertion violation occurs, depending on the implementation of the VHDL system or when the maximum time as defined by the language is reached.
Simulation algorithms: