HDL of synthesized design (synplify)

[martur]

hi,
i'm using synplify to synthesis my design.. but after synthesis, i don't find the VHDL netlist of the synthesized design. i don't know where to find it.

thank you in advance

 

[imbichie]

The netlist is in the form of EDIF, its with the extension " *.edn "
So just search in the project folder for this extension.

 

[wsong0210]

you can have the vhdl or verilog netlist, but these are generated for post-syn simulation.
You need to configure the software to generate these files.
The normal procedure only produce edf file as the output.

 

[martur]

thank you for your anwser

i know about the netlist .edf .. but i need the VHDL generated netlist. in the implementation options, i activated the option "write netlist VHDL output" .. but after sythesis, i can't find this file.. so i'm asking if there is an other solution to generate such file?? how to configure software to do it??
thank you in advance

 

[wsong0210]

the file may inside a sub-directory

 

[imbichie]

thank you for your anwser

i know about the netlist .edf .. but i need the VHDL generated netlist. in the implementation options, i activated the option "write netlist VHDL output" .. but after sythesis, i can't find this file.. so i'm asking if there is an other solution to generate such file?? how to configure software to do it??
thank you in advance

Do you mean the " *.vho " file, means the file after the place and route and timing simulation. If it so the file is in the project folder....