HDL Coding for synthesis

[uxarkirnamak]

Hello!

I's studying electronics and use Synopsys Digital Design Flow. I have read that the HDL coding style greatly affects the circuit that is being synthesized with Design Compiler and in order to design an efficient system one should know the right RTL coding style for achieving the best results! But, unfortunately, I don't know any good manual or book that provides Verilog coding guidelines for synthesis with Design Compiler. Please help to find or share information about that!

Thanx in advance!

 

[signbbs]

Hi, i heard of some book from Synopsys. You could find it from internet
<Advanced ASIC Chip Synthesis Using Synopsys Design Compiler,physical compiler and Primetime>