I miss the scriptor synthisis the Cusb IP core by synopsys.
Can you help me?
When I run the DC, it report many warnings as follow:
"Potential simulator-synthesis mismatch if index exceeds size of array. HDL -93"
"Variable 'a' is being read in routine .... , but does not occur in the timing control of the block with begins, there. HDL-180"
For HDL-93 warning, if you are sure that your index is never gonna exceed the size of array declared, then you may ignore this warning. As for HDL-180, variable or signal 'a' is not included in the sensitivity lists, you will need to fix this warning. At the end of the day, any mismatch can be captured by running gate-level simulation or formal verification.
Oh, Thx all.
My code as follow:
reg [10:0] a[3:0];
reg [1:0] b;
reg [15:0] c;
.
.
.
always @(a[0] or a[1] or a[2] or a [3])
reg [1:0] x;
begin x = b;
case( x)
.
.
.
default: c = {4'b0, a[x]} ;
endcase
when I compile, It infor me above information(HDL-180).
Why?
How can I revise it?
Tia