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HCE(hot carrier effect) risk for my deisgn

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chang830

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Hi,
I am desiging a mixed signal block for which the output buffer is an inverter chains to drive the 1pF load capacitor. The design is based on the 0.5um CMOS.I use the minimum length for the inverter buffer with speed considerations.But I have some concern that the minimum length will bring the hot carrier effects which will affect the life of the product.

It would be highly appreciated if some experts can shed some light on it.

Thanks a lot!
 

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