achundur
Junior Member level 1
Hi all:
I am using design compiler for synthesis of pipelined design and I am trying to clock-gate the pipeline registers. I made the registers load enabled using a enable input. The DC is inserting the clock-gating cicuitry but the enable pin of the clock-gating circuitry was directly connected to "enable input". But for other designs the enable input was coming from a control logic which was automatically inserted by DC. I tried " report_clock_gating -ungated -v " , but it is showing 100% clock-gating . It will be of great help if any one can give some suggestion on How to infer autonmatic clock-gating?
Thanks
I am using design compiler for synthesis of pipelined design and I am trying to clock-gate the pipeline registers. I made the registers load enabled using a enable input. The DC is inserting the clock-gating cicuitry but the enable pin of the clock-gating circuitry was directly connected to "enable input". But for other designs the enable input was coming from a control logic which was automatically inserted by DC. I tried " report_clock_gating -ungated -v " , but it is showing 100% clock-gating . It will be of great help if any one can give some suggestion on How to infer autonmatic clock-gating?
Thanks