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Having trouble Automatic Clock-gating using Design compiler

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achundur

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Hi all:

I am using design compiler for synthesis of pipelined design and I am trying to clock-gate the pipeline registers. I made the registers load enabled using a enable input. The DC is inserting the clock-gating cicuitry but the enable pin of the clock-gating circuitry was directly connected to "enable input". But for other designs the enable input was coming from a control logic which was automatically inserted by DC. I tried " report_clock_gating -ungated -v " , but it is showing 100% clock-gating . It will be of great help if any one can give some suggestion on How to infer autonmatic clock-gating?

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yx.yang

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Hi, I think DC does the right thing. DC will use the data enable at that DFF to gate the clock of that DFF. Such as the enb of DFF_A to gate the clock of DFF_A. As there is a enable from you module input, so DC will fed this enable input directly to the enable calculation logic the clock gate enable.
 

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