harvard or von neumann

[toomosta]

HI,
I know that this may be a silly question but i am new at computer architecture.
This image is for a single cycle MIPS processor i see that it has a data memory and instruction memory, do that it is harvard architecture ; because i read on the internet that mips is von neumann,
it's confusing.

 

[bigdogguru]

HI,
I know that this may be a silly question but i am new at computer architecture.
This image is for a single cycle MIPS processor i see that it has a data memory and instruction memory, do that it is harvard architecture ; because i read on the internet that mips is von neumann,
it's confusing.

While questions concerning processor architecture are far from silly, there is no clear question in your initial post.

Please state your question in a clear concise manner.


BigDog

 

[toomosta]

The question is the MIPS processor (it's image shown ) harvard or von neumann ?

 

[bigdogguru]

The question is the MIPS processor (it's image shown ) harvard or von neumann ?

Unfortunately, as often is the case and as technology progresses, the previously clear lines relegating a processor's architecture into either the Harvard or Von Neumann class have become blurred.

Many current processor designs blend these two distinct architectures to form a hybrid of sorts, such in the case with the Harvard Architecture, as it has evolved from a "pure" Harvard to a "modified" Harvard Architecture:

Harvard Architecture

Modified Harvard Architecture

The "blends" of processor architecture are often driven by the intended task or application of a specific processor design, such too is the case with the MIPS processor, as many of its currently manufactured designs are intended for embedded system applications.

The PIC32 is a good example, utilizing a licensed MIPS M4K core, its design incorporates both a nonvolatile Flash memory for instruction code and constant data and a separate volatile RAM memory for primarily data storage during runtime, although distinct separate address and data buses have been replaced with a Switch Bus Matrix module. The Switch Bus Matrix module effectively provides the programmer the transparent appearance of a unified linear bus, composed of a single address space and data bus versus the separate address and data buses implemented in the actual hardware.

The implementation of the Switch Bus Matrix seemingly contradicts the "pure" Harvard Architecture requirement that both the Instruction Memory and Data Memory have their own unique "zero" address locations. However, as the quote below indicates, this is not in contradiction with the "modified" Harvard Architecture.

Instruction and data memories occupy different address spaces

For pure Harvard machines, there is an address 'zero' in instruction space that refers to an instruction storage location and a separate address 'zero' in data space that refers to a distinct data storage location. By contrast, Von Neumann and "split cache" modified Harvard machines store both instructions and data in a single address space, so address 'zero' refers to only one thing and whether the binary pattern in that location is interpreted as an instruction or data is defined by how the program is written. However, just like pure Harvard machines, modified Harvard architectures with separate address spaces, but with instructions allowing locations in instruction space to be written or read as data, have separate addresses 'zero' for instruction and data space, so this does not distinguish pure Harvard machines from those types of modified Harvard machines.

The same Switch Bus Matrix also provides the ability to execute instructions from RAM memory, another contradiction with the "pure" Harvard Architecture paradigm.

I have attached both a video and PDF detailing the MIPS M4K utilized in the PIC32 device family, which clearly states:

Reference: Slide 3

The PIC32 employs the M4K® 32-bit core from MIPS Technologies. The M4K is a Harvard architecture based core. It contains separate Instruction and Data busses connected to the Bus Matrix.

I hope the information provided above helps clarify the issue.

BigDog

 

[betwixt]

Adding to that - I don't think it's possible to tell from the block diagram in post #1. It shows two distinct memory blocks which would suggest Harvard architecture but it isn't at all clear where the data and address paths are to the data memory.

Brian.

 

[Surender Reddy]

Can give me examples for both architectures?