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Harmonic-locking issue [CDR]

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jihrenee

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The CDR circuit has to detect the bit rate of the data without the harmonic-locking issue.
What is harmonic-locking issue it means here?
 

CDR circuit must have a clock with limited capture range such that it does not lock onto harmonics of input signal, as all pulses may contain harmonics of fundamental bit rate. One way is ILL or injection locked loop, another is PLL with Type 1 phase detector and other with type 2 Phase/frequency detector. Many ways to skin this cat such that VCO does not exceed harmonic of desired clock rate.
 
Thanks, by the way, what is the difference between false lock and harmonic locking?
False lock = locking failure
Harmonic locking = lock onto the wrong frequency
Am i right?
 

People who use XOR gates to mix signals get excellent PLLs but it is prone to capture range vs stability trade offs and easily locks on to harmonics. Using a Type II phi/f mixer prevents this.


If a VCO has the ability to reach the fundamental and harmonics while tracking an incoming variable frequency signal, one must be careful to filter the incoming signal before mixing as the mixer will also mix harmonics and the error can lead to mis-tracking of the wrong frequency, when using a TYPE I mixer such as an analog multiplier or the digital XOR gate.

Type II phase/freq detector. It uses edge counting methods using flip flops to determine which frequency is higher. So it is more reliable ( as long as there are no false triggers from noise.)


Or say you wanted to synthesize an ( ultra-accurate 1e-10 ) 10MHz clock from line frequency from a stable power source (They use Stratum 1 clocks) for say 50 or 60Hz. you could use a big divider on a VCO and if the VCO had a limited range around the 10MHz region scaled down to say 60Hz. then a TYPE I mixer may work fine. as the LPF will act as a BPF in the loop. But if the VCO had a wide tuning range say 3:1 then it could also lock onto the 3rd harmonic.

Not so with a Flip-flop UP-Down Edge counting Type II mixer. More sensitive to edge noise and asymmetry phase noise errors but immune to false harmonic locking.:roll::roll::lol::lol::-D:-D
 
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