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Harmonic analysis of mains voltage using ADC - input filter

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Member level 3
Mar 16, 2017
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For remote control of electrical equipment, we use a signal with a frequency of 250 - 1000 Hz, which is mixed with the mains voltage 230V 50Hz. I connected via a 230 / 6.5V transformer, MCU with ADC and with the help of tone analysis I can detect and decode control signals.However, the transformer is relatively large and has a relatively large consumption. I want to try another solution.

My solution
VR1 Safty
C1 C2 They reduce the voltage, with 50Hz reducing more and higher frequencies and providing a voltage resistance of 4000V
R2 small size resistance as safety fuse
D1 Safety
R7 ensures minimum current through C1, C2
50Hz Twin-T Norch filter suppressing 50Hz and thus increasing the weight of the higher frequency signal
C3 ,R1/R6 DC isolation and signal shift 0-3.3V
D2 Safety
R5 C4 LPF cutting frequency over 15kHz

According to the simulations, it works as I assume, but I wonder if I'm not exaggerating and it's not possible to throw something out of it?
In short, I am interested in your opinion and suggestions on what to do differently?
Thank you in advance

band retention.jpg


I guess this is a rather difficult task... because
* 250Hz is rather close to 50Hz, thus you need good filters.
* and 250Hz is quite a usual harmonic overtone when 50Hz is distorted. I guess a lot of mains loads will generate this 250Hz overtone. How do you handle this?

Mainly you get uneven multiples of 50Hz --> 150Hz, 250Hz, 350Hz ... as overtones.

I´ve never done powerline communication, but I guess higher frequencies may be less critical.


It's not my invention.
The signal is used by energy companies to distribute the load on the network
The signal, ie telegrams coded to them, are sent to the 110kV network and passes through the power network up to 230V
The range is tens of km, the standard says, the signal voltage level is 1 to 5% of the network voltage.
You're right 250 Hz is not actually used because it is a 50Hz harmonic. The lowest frequency used is 266.3 Hz
For interest, the bit is encoded as 500ms 1 and 330ms space 0.

Switched capacitor filters were commonly used for detection . often for example with LTC1060
Surprisingly, I tried to evaluate the signal directly from the transformer secondary 230/6,5V
Processing purely in MCU Goertzel algorithm and it works well in most cases
If the signal is very weak or extremely noisy, it is good to reduce the level to 50Hz and thus increase the weight of the signal.

you may well end up needing more protection given that all sorts of transients end up on the mains, 5W zeners in inverse series may well be a good idea. In parallel with D1

You may use Goertzel, or DFT...maybe an FFT.
I use the Goertzel algorithm because it is the most efficient for a given application on the MCU (STM32, for example STM32F03x).
The ADC measures voltage every 1 ms. I'm evaluating whether in the 120ms slot, the tracking signal has exceeded some weight. If yes, there is 1 in the given slot, if not 0. At the higher level, the structure of the telegram, its validity, and the received data are evaluated.
Both FFT and DFT could be used, but on a small MCU they would be computationally demanding.

>Btw: does the signal frequency depend on mains frequency or is it independent?
I don't really know
It is transmitted up to 110kV using a LC coupler with parallel coupling, but I don't know anything more

>Comb Filter ....?
I also have a design with a switched C filter LTC1060, it is not a problem to design and use a large and expensive HW filter, but it somewhat kills the magic of the DSP solution .
The first version contains only a small 0.5 VA transformer 230 / 6.5V and components from C3 to the right.
The transformer is, however, large and has an unnecessarily large self-consumption
Therefore, I designed a version with 2x 10nF 2000V, compared to the transformer have a higher impedance for lower frequencies. In other words, they increase the weight of the signal themselves.

Using a second / large hw filter then not makes sense to me, but using twin T NF (ie 3x C and 3x R) comes as a good idea, it's cheap and small. At the same time it can suppress 50Hz and thus increase the weight of the signal in front of the ADC and thus in the part processing the signal digitally, the ADC is 12bit

On the other hand, I have no practical experience with this, it is probably seen on the safety components in the connection of VR1, R2, D1, D2, who know what is unnecessary and what is not.

On the other hand, I have no practical experience with this, it is probably seen on the safety components in the connection of VR1, R2, D1, D2, who know what is unnecessary and what is not.
I think the original circuit is basically achieving the intended purpose of increasing the signal to noise ratio with 12 Bit ADC and digital post filter.
Using a higher resolution ADC would of course reduce the hardware filter requirements.

Regarding overvoltage protection, R2 can be increased to several kohm without significant signal attenuation. An additional series resistor between D1 and D2 can increase surge suppresion, presently there's a direct low impedance path between both, so input surge current is expected to load D2 instead of D1.


in post#1 you wrote: "we use a signal with a frequency of 250 - 1000 Hz,"

Now you say you do a sample every 1 ms.

There must be something wrong.


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