mkrtich.nazaryan
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Hi all,
I have a little time, and I'd like to learn a about HVL. But I'm new in this and need advice. I'm dealing with Verilog HDL (RTL level) and CMOS circuit design in transistor level. So which one is better?
1. OpenVera
2. e
3. SystemC
4.SystemVerilog
Thanks a lot.
I have a little time, and I'd like to learn a about HVL. But I'm new in this and need advice. I'm dealing with Verilog HDL (RTL level) and CMOS circuit design in transistor level. So which one is better?
1. OpenVera
2. e
3. SystemC
4.SystemVerilog
Thanks a lot.
Last edited: