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Hardware interupts in vhdl

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bashyamvikram

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Hallo all,

I am writing interputs for a fpga and dsp need to interact with a dual port memory shared dpram control in vhdl.
I have External IOs coming from the SPI bus on oneside to the fpag to be communicated with dsp and on the otherhand have a camera to the to the dsp.
So my intrups are like Havinf a FIFO being reset after everytime a FSM reads and writes the interrpts with dsp.

Now my problem is
1) I want to enable some particular interupts at a time and disable the others.
2)When make a masking with logical XOR function the other interupts coming from UART goes for a timeout.
3)When this is done the camera gets the signal but cant be controlled.

I use the following algorithm to deal with all asynchron inputs:
1. In event2reg_array_proc: save all inputs to parallel buffers “fifo_data_input_array”, each input(flag) should be put into separate buffer.
2. In reg_array2fifo_proc2: read each buffer serially and save them in a fifo “fifo320x32”.
3. In main FSM read the output from fifo and do the suitable processing, each cycle read out only one value, it should be one flag.

If you get some flags which remains in register even after processing, the reason can be:
1. In event2reg_array_proc: and reg_array2fifo_proc2:, if one flag (in buffer) has been written in the fifo, it should be cleared from the buffer. I use the “fifo_cnt” to control this. You can use simulation to check.
2. Line Camera sends the FRAME_VALID signal as same as the LINE_VALID signal, so you can get a lot of CAM2DSP_FRAME_SYNC_FLAG with Line Camera.


So can any one suggest any algorithm to enable particular interupts while the the camera is still communicating with DSP.
 

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