Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Hardware Design Engineer Needed - Full-time, Competitive Salary (Beaverton, OR)

Status
Not open for further replies.

cbennett

Newbie level 1
Joined
Jun 10, 2013
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
23
Hi Everybody,

I have an open position with one of my clients in Beaverton, OR. This client works partners with the best semiconductor, consumer electronics, multimedia and applications content developers in the world. Their technologies are present in the latest smart phones, tablets, and media players to wireless home and automobile features. A competitive salary and informal and open work environment are top features.

This position will be focused on the verification of sophisticated hardware designs that implement multiprocessor cache coherence. A mix of design and verification projects will be present in the future for this position.

My client is looking for this position ASAP, so local candidates (Portland, Seattle, etc.) will get heavy consideration.

I have more information for those that are interested - cbennett@protingent.com

This position is only open to Green Card and U.S. Citizens.


Position Title: Hardware Design Engineer

Position Description: Protingent Staffing has an exciting opportunity with our client in Beaverton. As a part of this group you will be a key member of a small team responsible for architecting, designing and verifying innovative cache coherent technologies used in many of Imagination's products.

Responsibliities: Supporting the definition and documentation of the verification methodology for a specific project or project components. Specifying and documenting the verification test bench. Owning and developing major verification blocks including: stimulus generators, monitors and checkers (scoreboards). Creating a test plan and generating tests and coverage code to support it. Ensuring closure of the coverage metrics. Developing scripts as needed to analyse results, check coverage and drive regressions. Occasional travel to Sunnyvale, CA.

Required Qualifications:
•Strong knowledge in HDL languages, RTL and logic simulators, HVLs such as System Verilog, VERA or "e".

•General knowledge of microprocessor architecture.

•An MS/BSEE or equivalent.


Additional Skills a Plus:
•Knowledge of cache architectures and cache coherence protocols.

•Knowledge in directed-random verification methodologies such as UVM/VVM/OVM.

•General scripting skills with Perl or equivalent.

•Prior experience with MIPS processors.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top