half-integer division with 50% duty cycle?

[twlin1]

Is that possible to get half-integer division divider with 50% duty cycle?
I want to get 160MHz from 240MHz, i.e., 240MHz/1.5=160MHz.
The methods realizing 1.5 divider I found are none of 50% duty cycle.

So, is it possible to get 1.5, 2.5, ... division with 50% duty cycle?
Thanks.

 

[SPIZERO]

Yes. That is possible to get 160MHz from 240MHz.
entity divider is
port(
clk : in std_logic; -- this is 240MHz clock
divided_clk : out std_logic;
);
end divider;
architecture behav of divider is
signal i : integer range 0 to 160000000:=0;
signal clk_160Mhz : std_logic:='0';
begin
process(clk)
begin
if rising_edge(clk) then
if i=160000000 then
clk_160Mhz <= not(clk_160Mhz);
i <= 0;
else
i <= i + 1;
end if;
end if;
end process;
divided_clk<=clk_160Mhz;
end behav;

 

[twlin1]

Sorry for not understanding code. Can SPIZERO help me draw the logic circuit ? Thanks. Orz

 

[SPIZERO]

Oh. I'm sorry. I thought that you need vhdl . But my code wasn't right.

with 50% duty cycle . maybe it is very difficult. You have to know delays of Latchs or Gates. And using glitch and delays to get 1.5 divided clock. But it is not good design. What about 33.33% duty cycle? it would be easier.

 

[erikl]

Check this thread!