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Half Bridge LLC Transformer

biswaIITH

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Hello all,

Currently i am designing a 2.0kW Half-bridge LLC with center tapped secondary for EV Applications

Input Voltage:- 400VDC Nominal
Output Voltage;- 40 to 60VDC
Output Current:- 35A

Fs_min:- 91 khz

Fs_resonant:- 151 khz

fs_maximum:- 225khz (Short circuit protection limited)

I am operating the converter equal to or below resonance region(boost mode) under all normal operating conditions. The converter goes into above resonance mode (Buck Mode) under some input disturbances depending on overall gain.

I have designed a transformer using PQ 50/50(N97) from TDK. It is not an integrated design i.e. resonant inductor is separate.

Transformer Designed

Flux Swing(Delta B):- 0.22 T

Primary Turns:- 15 (38 AWG/450 strands)...Secondary turns:- 3 (16 mil copper foil)..

Winding Pattern

First Layer:- 8 turns primary(Almost half Primary)

Second Layer:- 3 turns secondary( One half of center tap config)

Third layer;- 3 turns secondary (Other half of center tap config)

Fourth layer:- 7 turns of primary(Other half primary)


I have calculated theoretical loss around 10W using iGSE(improved Generalized Steinmetz Equation) for core loss estimation & sinusoidal Dowell's curve for winding loss estimation.

Is the t/f winding pattern & core size ok???

I would request experienced design engineer to give suggestion to improve transformer design

Thanks
 

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below resonance operation is inviting your mosfets to go bang all the time - redesign for always above resonance ....
 

biswaIITH

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But only above resonance is not a good region also due to light load regulation issue. It should be ideally a mix of both. The Maximum calculated R.M.S current rating for Mosfet is coming around 8-9 A under resonance which i think is manageable..However the output peak diode current is somewhat higher which can be a cause of concern!! Let me have a design change to see how rms current is varying with a mix of both modes.

Anyway thank you!!

i would also request other esteemed members to give their feedback.
 

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you are evidently un-aware of the hard switching failure mode of almost all mosfets in hard switched capacitive mode - let alone the losses and voltage spiking under these conditions ....
 

biswaIITH

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Hii.. I am very much aware of the disadvantages associated with capacitive mode. I am operating below resonance but all my operating points are well above ZVS boundry between inductive & capacitive mode.
 

treez

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In this course there are folders on LLC for you if you want…..
https://drive.google.com/open?id=0B7aRNbu3Fes4TU92Mkw3YlA3ams

Basically, you must produce a Vout vs frequency graph……..if you haven’t produced this then you will be in trouble.
I will send one soon here.
The well known app note from faichildsemi.com shows how you can easily plot this graph.

- - - Updated - - -

here is vout vs frequency graph attached

- - - Updated - - -

Also attached is an LLC design doc
 

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treez

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With the LLC, you should choose a magnetising inductance value as high as possible in order to reduce circulating current….however, there must be enough magnetising current to allow the VDS’s to discharge to near zero during the shortest dead time.
Also, when you have the vout vs frequency graph, you can soon see how much “m” value you need to be able to achieve your vout_nom from your vin_nom.
As always, if you have a fixed vin and vout, then you can make magnetising inductance high and still achieve it….however, the more variation there is in vout or vin, the more circulating current you tend to need to be able to serve the vin and vout range.
Your resonant capacitor should ideally be as high C as possible…….if its too small then the voltage on it can build up too quickly in overload etc…but then again………smaller C is easier to get at higher voltage rating…so it kind of works both ways….but just don’t make resonant C too small.

I always like to get the upper resonant frequency at least 10KHz above the peak of the vout vs frequency curve in the worst case vin and vout…..then if theres a tolerance in the components , you still don’t end up in the capacitive region.
You say it’s a battery charger…LLC is not usually liked for that because LLC is a voltage outputting topology….and if the Battery voltage is too low then the LLC could go into overcurrent…but I assume you have fast over current protection to mitigate this.
 

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If you are in ZVS, then by definition you are above the resonant freq of the ckt at that operating point ...

- - - Updated - - -

Also if you go over the gain hump to cap mode your regulation will lose "sense" i.e. it will go the wrong way ...
 

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Hello sir.. I have plotted out the Vout Vs F .. First i have adjusted the Lr,Lm,Cr ,Fr & turns ratio as per my design. I have attached the document of the results with 4 different operating points.View attachment Vout Vs F.pdf


Kindly review it once.
 
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treez

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looks good...but you need to put your values into the attached ltspice schem and run it and check for the zvs etc

- - - Updated - - -

remembering to change the frequency to suit...and a decent stab at dead time accuracy etc etc

.you can change it to split coil sec
You can also get the magnetsing current on its own

- - - Updated - - -

and if you want to be really brill...you can use a split resonant capacitor.....which reduces overcurrents during startup and transients
 

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The graphs are somewhat useful, remember you must control Fmin, such that you do not attempt to go too low in freq, i.e. in an attempt to get more current at 60V.

everything above the peak is inductive, ZVS ( sometimes called lagging ) switching, at the peak there is no spare current for ZVS transitions, below ( left of ) the peak is capacitive or traditional hard switching.

good luck

- - - Updated - - -

Your Tx design based on 0.22T at the min freq will likely make the core too hot

Try ETD54, or larger PM core

also you may find that the Cu foil gets pretty warm too

The lowest loss Tx designs use litz for the sec, well coupled to the litz primaries, often with teflon on the pri wires to give the required safety isolation
 

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Hello .. Now it seems that there is some margin available before the converter goes into capacitive mode. Should i go ahead with the design????

To have an improved safety margin , i will limit the maximum current i.e. 35A at around 56 V & will derate the current once voltage rises above it... i think this operation is well justified in battery chargers as current reduces as soc goes above 80-85% due to CV mode.

2) I will check with PQ 50/50 first ..if thermal issue arises ,i will go for a bigger core. i have calculated the core loss(around 2 W) using Improved generalized Steinmetz equation which takes care of non sinusoidal behavior of magnetizing current.
 

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PQ5050 N97 = 3.5W 100kHz, 100mT peak ...

make sure the freq can go high enough fast enough when a short is applied to the o/p. This is the biggest killer of LLC designs ...

- - - Updated - - -

is there any cooling avail for the Tx, apart from natural convection ...?
 

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I am using Infineon IC ICE2HS01G for controlling. It has a provision to increase the switching frequency faster In case of short circuit. I hope that should be enough

I am planning to do a complete potting of the transformer & resonant inductor . The charger will be IP67 Sealed. Apart from this ,i am planning to provide forced air cooling using a FAN
 

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what are you potting in? does the potting compound have high thermal conductivity ? or is it more of a thermal insulator?
 

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1.5W / m.K = 0.667 mK / watt, let us assume 10W per your prev post, and 1cm thru thickness and 3 x 3cm area as an approximation

this is 0.667 x 10W x .01 / 0.03^2 = 74 deg c rise

Of course you may have more area and less thickness - but it pays to look closely at these matters to avoid hot spot burn out in the middle of the Tx or choke ...
 

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hII.. m unable to import this file into Ltspice.. Do i need to change the format??New to Ltspice

- - - Updated - - -

looks good...but you need to put your values into the attached ltspice schem and run it and check for the zvs etc

- - - Updated - - -

remembering to change the frequency to suit...and a decent stab at dead time accuracy etc etc

.you can change it to split coil sec
You can also get the magnetsing current on its own

- - - Updated - - -

and if you want to be really brill...you can use a split resonant capacitor.....which reduces overcurrents during startup and transients
hii..I am using split capacitor configuration with clamping diode.... M unable to import this simulation file into Ltspice..Do i need to change the file format??
m new to Ltspice!

Kindly ,reply!!!
 

treez

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also, the course i sent you in #6 has some folders on how to quickly get going with LTspice
 
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