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Half-Bridge 0-30V, 0-20A Feedback loop problem

paladyn

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Welcome,

Plans to design an adjustable power supply based on the SG3525 controller with the possibility of voltage regulation ~ 0-30V and current ~ 0-20A.

I have a working power stage, which is able to give over 20A at 30V, while I have a problem with the implementation of the feedback loop.

I use an external LM324 operational amplifier which realizes two feedback loops - voltage and current.

I used a type 3 compensator but the effects do not fully satisfy me. The test load is about 1ohm and at 5V and 5A the transformer is quite loud, as if some of the control runs have disappeared and the asymmetry on the transformer core has been created. at 15V and 15A everything is working quietly.

Can you direct me how the feedback loop should look like so that it is possible to realize my assumptions?

There is a lot of impulse power supplies on the market that work very well in a wide range of output voltages and are very quiet and have very low output noise eg gophert-cps-3205
 

Easy peasy

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may not be feedback loop - per se - if you have a buck derived converter ( includes, half bridge, full bridge, push pull ) then you will need slope comp in the control if you exceed 50% of possible gate ON time ... you have not given enough info in your posted question ... assuming you are using current mode control - if voltage mode it is likely that your output LC res freq is quite low and your control will need feed forward to balance that - else the control loop will need to be 5x lower than fres of the o/p filter ...
 

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SG3525 means voltage mode, there should be no need for slope compensation, neither with average current control.

Did you analyze feedback loop transfer function and particularly and phase margin?
 

paladyn

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Easy peasy
I place the PCB diagram of the power part and the PCB diagram of the control part

The resonant frequency of the LC filter is fairly low at 184Hz.

In general, I counted the compensation factors in the following way:
Cout = 3 x 1000uF
Total ESR = 8.3mohm
Lout = 250uH
fESR = 6392 Hz
fLC = 184Hz
fz1 = fz2 = 184Hz
fp0 = 260Hz
fp1 = fESR = 6392Hz
fp2 = 1/2 fsw = 20kHz
frcoss = 1/10 * fsw = 4kHz
Vramp = 2.8V
Vin = 43V (output voltage after diodes)
fsw = 40kHz


C1 = 30.6nF -> I used 33nF
C2 = 42nF -> I used 42nF
R2 = 28,3kohm -> I used 27kohm
C3 = 297.6pF -> I used 300pF
R3 = 600ohm -> I used 560ohm

Maybe I just wrongly calculated possibly bad values for calculations?
 

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Pin 10 can be used for cycle by cycle current limiting on the 3525 & 3525A ....
 

paladyn

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FVM
Did you analyze feedback?
No, because I do not have that knowledge. The only hitching point is patterns and calculations and live tests.
 

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shunt resistor should be before the o/p filter caps - else you have an extra delay in the current loop you don't need ...

- - - Updated - - -

the current loop should be much slower ( 5x ) than the volt loop so they don't try to fight each other at the same freq at the crossover point. Also see post #2

- - - Updated - - -

I do not see the feedforward part of the V loop aimed at the output filter - given the o/p filter is 183Hz, tricky to have the V loop faster than this ....
 

paladyn

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Easy peasy

The diagram is a 47uH choke, but currently I run tests on a 250uH choke. I thought that too small inductance is a problem.

It will apply the current loop 5 x slower than the voltage, but the issue of the frequency of the voltage loop remains.

Could you tell me what the frequency of the voltage loop should be?
 

paladyn

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start with 3x slower than the o/p filter ...

Okay, but please guide me from which frequency the crossover loop should be 3 times slower?

Should fcrossover be 3 times slower than fp0?
Should fcrossover be 3 times slower than fLC?
 

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fLC - which is the only freq of interest in the power ckt ( apart from output ESL/ESR with C i.e. self res )
 

paladyn

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I carried out tests for the new frequency fcross = 1/3 fLc -> 61Hz. Screen shots of the oscilloscope load approximately 1ohm. Measurement made at the output of the inverter.


DS1Z_QucikPrint1-2.5A.png
2.5A Load
DS1Z_QucikPrint2-5A.png
5A Load
DS1Z_QucikPrint3-7.5A.png
7.5A Load
DS1Z_QucikPrint4-10A.png
10A Load
DS1Z_QucikPrint5-15A.png
15A Load
DS1Z_QucikPrint6-20A.png
20A Load

You can see that the loop is unstable, the transformer stops squeaking only at 7.5A load
 

asdf44

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Type III compensation should follow standard practice: two zeros placed in front of the LC cutoff, 2 poles following later. Intersil has the best app note https://www.renesas.com/us/en/www/doc/tech-brief/tb417.pdf. I'd strongly suggest simulating, if only some pieces. For example LTSpice will give you a great bode plot of your error amplifiers so you can check that you implemented the poles and zeros correctly.

Note that you don't need type III. Dominant pole can be ok too (set a single pole <1/5th or so of the LC) and may be easier to get up and running.


I don't necessarily see instability yet. I see unexplained ripple and scope noise. What's input voltage look like, what's a step response look like.


Did you describe how you implemented your current loop? There are many options in a voltage mode converter. What's its output of the current error amplifier going too?
 

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looks like your power supply source is running out of steam and supplying ripple to the input ...
 

paladyn

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I based all calculations of the loop on two sources:
1. Switching Power Supplies A to Z Sanjaya Maniktala
2. https://www.biricha.com/uploads/8/9/8/0/89803127/foundations__part2.b__2.pdf

From what I read the type III compensator improves the stability of the loop because it includes fESR.

With loop simulations I had a lot of problems, I do not know if you need to simulate the entire converter model or just the operational amplifier itself. However, I was able to find the SG3525 model and draw the entire converter model. Of course, for each calculated hardware configuration, using the above-mentioned sources, the inverter was excellent.

Currently, it tests only voltage loops to not mix. The noise that can be seen on the oscillograms is actually very large. Perhaps this is due to the bad running of paths.

Converter diagrams are in the post No. 4.

If I understood correctly a single pole (fp0?) Should be <1/5 of the LC point, and what should be the frequency of the fcrossover control loop? 1/10 of frequency switching?

As for measuring the output from the error amplifier, it is also strongly noisy. I do not know if this is due to the measurement of the oscilloscope where the probe does the antenna, or maybe the problem is PCB paths.

I will add photos of PCBs to make it easier to see how everything is designed

Thank you for your help and I am asking for your understanding, this is my first converter with feedback.

IMG_20190615_232329.jpgIMG_20190615_233228.jpgIMG_20190615_233240.jpgIMG_20190615_233253.jpg

As you can see the tiles have already gone a bit, the crooked elements of the compensator result only from a huge amount of soldering. In the testing phase, I did not care about aesthetics.
 
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Easy peasy

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you cannot probe the error amp output without introducing noise - or using a 10k resistor on the probe tip - there is a filtering effect - but you can see some thing...

- - - Updated - - -

Also - your bridge rectifier will need heatsinking ...

- - - Updated - - -

your fets are kinda a long way from any decoupling caps - this will create turn off noise ... and overvolt spikes...

- - - Updated - - -

Is there a schematic?
 

paladyn

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Below are still oscillograms from the primary side:

DS1Z_QucikPrint1.pngDS1Z_QucikPrint2.pngDS1Z_QucikPrint3.pngDS1Z_QucikPrint4.png
U_DS upper transistor

DS1Z_QucikPrint1.pngDS1Z_QucikPrint2.pngDS1Z_QucikPrint3.pngDS1Z_QucikPrint4.png
Transformer

I know that long paths are not conducive to low noise, but it seems to me that it looks pretty good. I saw much worse waveforms on the Internet and the inverters worked properly.
 

asdf44

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Yeah the switching waveforms look ok.

Another suggestion: Run open voltage loop. Reconfigure the eamp as a fixed voltage follower. This will isolate eamp problems from other problems.


For simulation use LTSpice and start with the UniversalOpamp2 - a model with supply rails and parameters for gain-bandwidth etc.
 

paladyn

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asdf44
When I find a moment, I will try to carry out such an experiment by setting rigidly pwm.

Easy peasy
I just meant the primary side waveforms. Because the secondary side waveforms look weak to me even with a small load.
 

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