mrinalmani
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I recommend this. Because adding capacitors or slowing down dV/dT will/may create additional loss, but in the (opposite) MOSFET.Another option is to use a bipolar gate drive.
I don´t agree.If you refer to the 1st or second photo, you will notice that the Vds voltage transition only happens after about 200ns when the gate voltage has fallen down, this is because of the dead band.
You need a V_BUS_capacitor. If it´s a true DC-bus, then I recommend an electolytic bulk capacitor plus a fast ceramics capacitor very close at each highside_mosfet_drain.It read 50mA almost independent of bus voltage (30V to 300V). I don't know how accurate this reading would be because the current pulses will be rather narrow and the multi-meter may show erroneous reading.
The SI8273 is a bipolar driver.Also, I understand that bipolar drive would be a great option.
Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.IMHO: Eoss is the total energy stored in the gate capacitors. But I don´t think the whole energy is dissipated within the MOSFET. (Energy should never be dissipated by capacitors, anyway). The energy should be dissipated in the series gate resistance and in the gate_driver_resistance. so it will be divided in two parts.
Interesting. Note that in the datasheet, Eoss only changes from 1.1uJ to 1.6uJ as Vds increases from 30V to 250V, due to the severe nonlinearity of Coss. If your dissipation were entirely due to Eoss, then you might expect your power dissipation to rise by about 50% over that range. This would mean that your supply current would actually decrease as you increase Vds from 30V to 250V.Today I also measured the DC bus current using Fluke-115 multimeter in DC current mode. It read 50mA almost independent of bus voltage (30V to 300V).
You are correct. A little sketch helped me to see that the very most part of the energy is dissipated by the mosfet.Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.
Using Eoss for the loss estimation of transistors switching in bridge topology will seriously underestimate losses, due to the capacitance nonlinearity. A simulation with trustworthy nonlinear Coss model can show you why. While Vds is low and C(Vds) is low, most energy is dissipated by the opposite switch at Vbus-Vds.Eoss is energy stored in Coss, the drain source capacitance. It is always dissipated by the FETs, unless some amount of soft switching occurs.
Yeah, I just realized this, see above. Also confirmed it with a simple SPICE simulation.Using Eoss for the loss estimation of transistors switching in bridge topology will seriously underestimate losses, due to the capacitance nonlinearity. A simulation with trustworthy nonlinear Coss model can show you why. While Vds is low and C(Vds) is low, most energy is dissipated by the opposite switch at Vbus-Vds.
The device datasheet gives a plot of Eoss vs Vds, it's about 1.6uJ at 250V. So with no load and 100kHz, you should see about 0.32W per FET of dissipation. Not enough to account for what you're seeing.
Cross conduction due to miller effect is plausible, since the Qgd of these FETs is greater than Qgs. In such a case, you must limit the dv/dt of the switching node. Ironically, one way to do this would be to add capacitance there, and your load inductance would aid in soft switching (on half of your edges, anyways). Another option is to use a bipolar gate drive.
What is the measured power observed from your PSU?
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