Guidelines for I/O pad simulation

[pbs681]

Hi,
Other than driverbility(ioh&iol and tr tf)- output pad and Vih&Vil- input pad, what else important simulation need to be done for the design of io pad design.
thx

 

[beckwang]

Re: I/O pad simulation

noise is the important factor in the design of output pad ,
and driver ability , esd protection is also the important issue

 

[pbs681]

Re: I/O pad simulation

thx beckwang. Do you have any idea on how to model the noise and also the ESD simulation for the pad. I think it is pretty hard to model the ESD as the ESD event normally occur when our IC is not functioning.

 

[rajesh13]

Re: I/O pad simulation

You also need to run simulation for maximum frequncy of operation for both input & output buffers.

For Output buffer, Tr/Tf will deside the max freq.

You can also run DC current consumption simulation.

 

[piao]

I/O pad simulation

some people use big capacitor to model the ESD, you should refer to that kind of ESD model. then to decide how to run simulation for ESD.

 

[pbs681]

Re: I/O pad simulation

Thank piao. Do you have any reference for this big capacitor model or other method?

 

[dumbfrog]

Re: I/O pad simulation

extract the layout and rerun the simulation both with and without the package inductance. u will find something interesting.

 

[pbs681]

Re: I/O pad simulation

Hi dumbfrog,
This is my first task on the padframe design. I don't know what do you mean by package inductance. Appreciated if you could explain more on that. i.e how to include that package inductance into our simulation.

 

[dumbfrog]

Re: I/O pad simulation

I/O means circuit+ESD+package

Package is the bonding inductance, contains RLC for vddio, vssio, and output. You can get these numbers from the package designer or package specs. Once you get the RLC numbers, you should put it in 5 or more segments. The simulation is like running SSO, but now just one output switching. This is much more closed to real environment.

For SSO, just do a search on "GOOGLE", lots of papers on this topic. :lol: .... me...me :lol: too lazy to explain.


0.09 points away for 100.

 

[alanbrooke]

Re: I/O pad simulation

In fact, The ESD may not be simulate by hspice.
For the I/O design, you need also take care of the propergation delay, slew rate, and drive capability.

 

[alanbrooke]

Re: I/O pad simulation

The HSPICE can not simulate the break down of a diode, so you can not use HSPICE to simulate the ESD,
I don't know if any EDA tools can do the simulation.

 

[rajesh13]

Re: I/O pad simulation

Yes, you can simulate ESD event but only HBM & MM (human body model & machine model). So use the RCL compenent values as given in the model and connect it as mentioned. Also use .ic (initial condition ) statement to initialise for charged capacitor.
Then use any simulator (hspice, eldo, spectre etc)

 

[abhishek.k]

Re: I/O pad simulation

Rajesh is right!! You can simulate HBM and MM events for Non breakdown clamps.
For exmaple , in Hspice this works for HBM 2kV:

SUBCKT HBM NEG POS
RR1 NET20 POS 1.5K
LL4 NET20 NET5 7.5u
CC5 POS NEG 10p IC=0
CC4 NET20 POS 1p IC=0
CC0 NET5 NEG 100p IC=2K
.ENDS HBM

 

[selvaraja]

Re: I/O pad simulation

generate TLP pulse the simulate esd event

 

[dgnani]

Re: I/O pad simulation

The HSPICE can not simulate the break down of a diode, so you can not use HSPICE to simulate the ESD,
I don't know if any EDA tools can do the simulation.

Yes, you can simulate ESD event but only HBM & MM (human body model & machine model). So use the RCL compenent values as given in the model and connect it as mentioned. Also use .ic (initial condition ) statement to initialise for charged capacitor.
Then use any simulator (hspice, eldo, spectre etc)

Rajesh is right!! You can simulate HBM and MM events for Non breakdown clamps.
For exmaple , in Hspice this works for HBM 2kV:

SUBCKT HBM NEG POS
RR1 NET20 POS 1.5K
LL4 NET20 NET5 7.5u
CC5 POS NEG 10p IC=0
CC4 NET20 POS 1p IC=0
CC0 NET5 NEG 100p IC=2K
.ENDS HBM

Very few design kits have high current models for their ESD devices; w/o such models you can barely get qualitative behavior of your circuitry; e.g. think of snapback protection. Most ESD models are only useful to simulate leakage and load of the ESD devices

 

[leo_o2]

Re: I/O pad simulation

For ESD simulation, thermal effect should be included in modeling for damage emulation.