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Guidelines for designing a standard cells in custom ic layout...

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dgnani

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well perhaps you should post this on the digital design forum...

the guidelines mostly depend on the router capabilities so mention what the target router will be
 

dick_freebird

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Every standard cell library used to start as a collection of
hand laid out cells. Although I have worked with some folks
who use compiler based meta-libraries and port the one
master to many foundry flows.

The real keys are uniform placement of the pins, and cells,
on a regular grid, and ensuring that cells are buttable in
all orientations (half-spacing clearance to boundary). A
particular placer / router will need dimension and pin
location info tabulated in useful form. The cells may need
routing-specific features (prBoundary, pins/texts, etc.)
that a custom cell may not require.

I've custom-drawn "standard" cells and then hand routed
tens of kGates random logic. I wouldn't recommend it, but
standardizing cell layouts does have benefits even to a
primitive physical design approach.
 

Rubinms88

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Can anyone explain how we can find the area of diffusion of transistors if width & length is given in case of standard cells??
 

dick_freebird

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You can approximate it from groundrules
L=(contact_gate+contactL+contact_N+)
W=Wdrawn
times two for a solo FET.

Problem #1 is that stacked or paralleled devices often share a S/D
region so the simple way overestimates area.

This would more appropriately be done by a simple DRC runset,
where you might do things like reject well tie areas as non-
reverse-biased, non-yield / non-leakage-detractors.
 

Oveis.Gharan

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Every standard cell library used to start as a collection of
hand laid out cells. Although I have worked with some folks
who use compiler based meta-libraries and port the one
master to many foundry flows.

The real keys are uniform placement of the pins, and cells,
on a regular grid, and ensuring that cells are buttable in
all orientations (half-spacing clearance to boundary). A
particular placer / router will need dimension and pin
location info tabulated in useful form. The cells may need
routing-specific features (prBoundary, pins/texts, etc.)
that a custom cell may not require.

I've custom-drawn "standard" cells and then hand routed
tens of kGates random logic. I wouldn't recommend it, but
standardizing cell layouts does have benefits even to a
primitive physical design approach.
Hi dear dick-freebird.
You said that you have custom-drawn standard cell.
It seems you are an experienced one in digital deisign.
What is the begining of the flow of creating a cutom standard cell.
Is it possible to name at first the steps of that flow?
I am will be so greatful from your answer.
Thanks in a dvance.
Alireza
 

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