Guessing CMOS process node wrt to IC power supply

[davestew]

Hello all,

I am attempting to guesstimate the CMOS process used in off-shelf ICs (e.g. ADC, opamp, etc.) based on the power supply value listed in their datasheet. It usual practice not to mention it in their datasheet - they will usually mention that the IC is made in CMOS process but that is all they will say. Therefore, since the power supply (range) scales directly with the technology (process node), at least concerning the core transistors, one should be able to guess the CMOS process node that was used to fabricate the IC. I am aware that it is not always as easy it sounds - it could be that all IOs are of the HV flavor and they have regulators/LDOs for the core power supply, etc.

Example: Usually ICs that have a typical power supply of 1.8V are of 0.18um cmos process. Right now I am trying to determine what is the process node for all ICs whose power supply is listed as 2.7-5.5V.

I searched the web for a comprehensible table of [CMOS process node vs power supply voltage], but alas no success. I would think such info would be easy to find (can't be top-secret, at least of old techs). It anyone can help me out, it would be much appreciated.

Thanks
-Dave

 

[Dominik Przyborowski]

Each cmos process provides transistors with different gate oxide thickness for different supply voltages. Also an HV options axists with LDMOSfets operating with supply as high as hundreds volts.

 

[dick_freebird]

Once the fabs started producing DGO (dual gate oxide -
core and I/O most usually) flows this became a lot more
difficult to pin down. You would see 5V-capable I/O (thick)
devices on nodes down to about 0.25um and 3.3V capable
persists at 0.13-0.18. And on SOI you can (I have) made
6V reliable parts using "3.3V" transistors and a lot of cascode
elaborateness (analog often makes this choice anyway).
The relation of core to I/O oxide thickness is sort of an
arbitrary one, other than that the I/O device needs to be
well (enough) driven by whatever core Vdd min, is. One
fab might marry 0.25um / 2.5V core with a 0.6um / 5V I/O
and another, 2.5 core and 3.3V I/O (not a great choice,
a pretty marginal step up, but this is about the business
and not so much about engineering-in-vacuum preferences).

Drain engineering has also had a lot of impact (made foggier)
the relation of L to BVdss / rec max Vdd ratings. I remember
when 1.2um gave way to Ldd engineered 0.8um gave way to
struggles at 0.6um, in the 5V logic / mixed signal space. Now
everything's got halo implants and multi-implant multi-angle
LDDs in some combination or other, and they all hide the true
nature and details of their reliability position, qualification
conditions and lifetime @ use-model from view by anyone
not under NDA and looking like money.