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GTECH Simulation models

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ekForums

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Hi,
I use the following command in design compiler to write the generated netlist in VHDL format (before any technology mapping):

write -format vhdl -hierarchy -output $filename

The generated VHDL file contain GTECH models that are defined somewhere else in the installation path.

My question is, is there anyway to force Design Compiler to include the definitions of the used GTECH models in the same VHDL file as the design itself?

Thank you.
Eliyah
 

kornukhin

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GTECH is an internal DC's view. I never heard about any kind verilog model for it.
As I know if you write unmapped netlist and it contains *SEQGEN* elements, DC can't read it back.
 

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