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Grounding of optocoupler PCB (Ground_A, Ground_B and Earth)

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andres.m

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Hi guys,

I have been googling for a while and found lots of generic advice. However, I am struggling to narrow all down to my specific case. I know this is a complicated topic, but any help would be greatly appreciated.

In the attached schematic:
- There are 8 input signals referenced to SIDE_A_GND. This is the signal side of the circuit. All inputs are 3.3VDC signals from a microcontroller. Noise immunity is very important here. Before installing the optocoupler, the power side was causing the microcontroller to reset.
- The inputs signals are isolated and boosted to 12VDC using a TLP2955. The output side of the optocouplers is referenced to SIDE_B_GND. This is the power side of the circuit. SIDE_B_GND is connected to the GND of a high power 48VDC@42A supply.
- The opto-isolated signals are used to trigger MOSFETs at 5kHz.
- I normally wire the mounting holes to a metal case to get sort of a Faraday cage (e.g. see diagram before the 'Ground Vias' header under
https://blog.upverter.com/2019/11/07/pcb-grounding-techniques-to-do-and-what-not-to-do/) . This is labeled as 'Earth' is the schematic (Although 'Chassis' may be a better name).

I am building a two layer PCB, but I am unsure on how to layout the copper fills for grounding:
- Option A: Make a large fill on the top layer for SIDE_A_GND and a large fill on the bottom layer for SIDE_B_GND? Leave Earth unconnected.
- Option B: Make two large fills in the bottom layer (one on the left for SIDE_A_GND, one on the right for SIDE_B_GND). Leave the top layer only for routing without fills. Leave Earth unconnected.
1611036732250.png

- Option C: Make large fills on both the top and bottom layer connected to SIDE_B_GND. Use a large track from the screw terminal splitting into 8 tracks towards each opto (star connection). Leave Earth unconnected.
1611037394161.png

-Option D: Use a star grounding for both SIDE_A and SIDE_B and pour fill the rest of the top/bottom of the PCB with earth.
1611037732530.png


I tried to strike a balance between providing detailed information without overflowing the post. If other important details are missing, please let me know.

Thanks a lot for any tips.

Andres
 

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KlausST

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Hi,

There are several ways.
I think the most simple and generally good way is: both GND planes on the bottom. No GND plane amd no copper pour on the top.

Bottom: really solid, best without any other signals, no split .... GND plane.

Copper pour: I'm no friend of it. It more "looks good" amd makes someone "feel good" than it technically is.
I'd say. 100% solid on one layer (indeed it makes not much dufference whether Top or Bottom) is much better than two layer with 95%.

It does not matter whether the signal frequency is 5Hz, 5kHz or 5MHz .... the enemy (EMI / EMC) always is (very) high frequency. Both for sending out and receiving. Thus an EMC_rugged PCB layout is similar as a HF design.
Any signal needs a return path. Best if the return path is the GND plane on the opposite side. Any cut in the plane will create an impedance jump, may cause delay, echo and ringing and in most cases leads to an "antenna" for sending out and receiving noise.

I"d add some capacitors to "HF-join" both planes. Maybe up to 1nF. Depending on voltage sources it needs to be "Y-rated" safety.
Depending on the case, the case connection, the (noise) current flow there will be an optimal place. On one edge, the other edge or centered.
Thus it may be a good idea to add three (or two, or more) places, but only assemble one. The EMC test will show which place is the better one.

Also consider to install a high ohmic (high voltage rated) resistor between both planes to generate a discharge path for ESD. Placement is uncritical.

Your drafts are good. But you may also show us your true PCB layout before sending it to the PCB manufacturer.

Klaus
 

andres.m

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Hi Klaus,

Thanks for all the tips. Really helpful.
I have attached the PCB, hopefully I understood your post in the correct way.
- I have placed 2x1nF Y-rated capacitors (C1, C2) joining the two planes.
- I have also placed a 10Mohm resistor (R9) between planes.
- I have placed the earth around the board with 4 connection points to the chassis (mounting holes). As you suggest, I will test and connect only one.

I appreciate any additional feedback on the PCB.

Just to round up my understanding:
- What are the criteria to decide on the the number and location of the capacitors (C1, C2)? If I understood correctly there is no critical requirement for R9.
- I have seen other forums where the earth/chassis is connected to the power supply ground in a similar fashion (via capacitor and high resistance resistor). Is there any rule of thumb to decide for/against this connection?
- I have been reading https://www.analog.com/en/education/education-library/linear-circuit-design-handbook.html#, specially chapter 12. Would you recommend another resource that has a similar practical/hand-ons approach?

Thanks again for your time,

Andres
 

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Hi,

Isolation:
There is a wide isolation under the optocouplers. Use the same isolation width all around the GND polygon.

There is an IC .... i recommend
* to use a power supply capacitors: one big bulk capacitor and one fast ceramics capacitor at every supply pin of every IC.
* to use input protection (ESD)

Some traces are unnecessary narrow.

Klaus
 

andres.m

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Hi,

Isolation:
There is a wide isolation under the optocouplers. Use the same isolation width all around the GND polygon.

There is an IC .... i recommend
* to use a power supply capacitors: one big bulk capacitor and one fast ceramics capacitor at every supply pin of every IC.
* to use input protection (ESD)

Some traces are unnecessary narrow.

Klaus

Thanks Klaus,
Noted.
If you have the time, it would be great to hear your answers to the three questions at the end of my previous post.

Cheers,

Andres
 

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