GPIB interface design - about active and passive pins...

[vahidkh6222]

gpib interface ic

hi all
My project is designing an IEEE 488.1 (GPIB) interface on FPGA.
But I don't know exactly what is the difference between passive and active signals and how can I implement each of these signals on FPGA in practice. I mean the circuit or any idea that I can make a signal active or passive.

 

[IanP]

ansi/ieee 488.1

In the GPIB I wouldn't name pins (lines) passive or active ..
In this standard there are 8 Data Lines (DIO1 to DIO8), 3 Handshake lines (NRFD, NDAC and DAV) and 5 Bus (interface) Management Lines (ATN, IFC, REN, SRQ and EOI) (.. + 8 GND lines ..), and all these lines are "active" ..
More details on these signals can be found at:
**broken link removed**

Regards,
IanP

 

[drwho78]

gpib+fpga

The IEEE 488 standards have already been posted:

**broken link removed**

 

[vahidkh6222]

gpib device setting srq code

dear IanP and drwho, tnx for you response, but maybe i didnt explain the problem well....

My problem is beyond these. I have to design a complete IEEE 488.1 interface board by using FPGA. Controller, talker and listener should be implemented on a single FPGA IC. In designing machine states of functions (T, L, PP, DC,…) I have to be able to differ between active/passive signals IN PRACTICE.

ANSI/IEEE Std 488.1-1987” standard page 11 part 4 says:

“4) A remote message can be transferred in one of four ways:
a) An active true value being sent is guaranteed to be the value received and the device need not allow it to be overridden
b) A passive true value being sent is not guaranteed to be the value received, and the device must allow it to be overridden
c) An active false value being sent is guaranteed to be the value received, and the device need not allow it to be overridden
d) A passive false value being sent is not guaranteed to be the value received and the device must allow it to be overridden “

Active/passive concept used because there may be more than a device on the bus and send a signal.In order to avoid conflict active/passive would be useful. In the state machines it is said clearly in the standard that a signal should be active or passive. For example, when it is said that in SH function, at SIDS state, DAV should be send PASSIVE false but in SGNS state it should be send ACTIVE false(page 15); my problem is how I can make it active or passive in my VHDL code for FPGA? How can I make a signal to be sent active or passive?

thanks in advance

 

[vahidkh6222]

gpib interface design

why dont anyone answer?

 

[echo47]

gpib design vhdl

Probably because nobody knows the answer.
I looked briefly at the IEEE standard, and the active/passive stuff makes no sense to me.

Here is newer version IEEE Std 488.1-2003 - maybe it will help somehow.

 

[vahidkh6222]

active and passive signals

tnx dear but...
i can not get the file, it says that the file is no more available

 

[Cluricaun]

fpga gpib

Hi

**=tt
Then use free mirror
Cl

 

[drwho78]

pines gpib

tnx dear but...
i can not get the file, it says that the file is no more available

File downloads fine. I just checked it.

Added after 49 minutes:

Here is an IEEE488 tutorial from HP. It does not mention anything about passive or active.

Attachments removed
/Cl

 

[mystery]

gpib fpga

tnx dear but...
i can not get the file, it says that the file is no more available

File downloads fine. I just checked it.

Added after 49 minutes:

Here is an IEEE488 tutorial from HP. It does not mention anything about passive or active.

The above files can be download from the following url.
**broken link removed**

 

[hill]

fpga gpib




The links above were provided in this thread. Somehow they are no longer working. Can someone help please?

Added after 20 minutes:

Oh well I am particularly interested in IEEE Std 488.1-2003 link...