Got a simulation problem when add a Vpulse source (cadence)

[David Chiang]

Hi,folks.

I designed a fully differential OP for Switched Capacitor amplifier.

As a test , I connect the op like this .

A amplifier which voltage gain is 5 (C1/C2=100fF/20fF)
And the result on output node is


I think it's a correct result.

But after I add a Vpulse source which doesn't even connect with any node and any branch. Like this

Then I got a different and weird result.


Can somebody help me to resolve this problem ?
Or I can't design a Switched Capacitor amplifier.
Thx.

 

[BradtheRad]

Not that I know for sure, but the program has trouble making the new isolated Vpulse source co-exist on the same layout with the first circuit.

1.

Could there be a chance the time step needs adjusting?

2.

I do not see any parameters for the isolated Vpulse source. If you were to fill in typical parameters for it, the results might get back to normal.

Did you plan to hook it up to the existing circuit? If so then you might as well go ahead and do so.