Good OPA for bandgap reference circuit

[cliffj]

Hi, guys

As you can see in the schematic, there is an OPA used in this bandgap design. The post silicon validation data I have for similar design is basically fine. I mean it could work well by varying power supply or temperature (<5mV from 2~5V and 0~100degree). But the problem is that the output voltage of bandgap is not the same from die to die. (1.1 ~1.3 for example). Does anyone have the same expericence on this issue? I mean, like OPA offset, or the PSRR, or there should be a low impedance buffer of the OPA used etc... Please helps me to solve this problem.

cliff

 

[tlihu]

There are quite a lot of factories that affect the outputs of the BGR, such as the device mismatches, process variations of Rs'. Sometimes trimming circuits are added for fixing this kind of problem.

 

[Fom]

M12 connection looks very strange. I think it shold be something like power-on-start-up. I don't think this schematic should work at 2~5V. If voltage between source and gate of M12 will be more than Vthp it will be ON. But it possible when Vcc is increased but Vout is not change. In short when Vcc-Vout>2*Vthp. Vout followed by Vcc.

 

[rfsystem]

If simulation shows that

VDD-Vth,p-Vdsat,p-Vth,p < Vbdg

then M12 is proper designed. Otherwise simulation would highlight this effect. A source of the wafer spread could be the impact of contact resistance or emitter resistance of the k*T loop. So make an analysis of the k*T loop including the spread on contact resistance and emitter reistance

 

[clear]

may be offset voltage of opamp.

therefore, You should design low offset opamp.(bipolar opamp or large size cmos opamp)

 

[xwcwc1234]

I think it is due to many factors , such as opamp offset , dc gain , bandgap voltage variation .... etc. So in the literature, there are some papers discuss the curvature compensation for bandgap voltage.

 

[ambreesh]

I have had same exprience.
Problem is majorly at the foundry end. The process may not be very stable.
Problems could be following:
1. Mismatch in devices
2. Opamp Offset
3. Sheet resistance variation of resistors
4. Stresses induced when die is cut and also during packaging

Usually this is reffered as intial accuracy of a reference

 

[fmgay]

In my opinion, VO should be about 3 time 1.2V, that is 3.6V or above it for the low temperature coefficient.