Global skew confusion

[pradeeppiskala]

let's assume A is talking to B

latency from clk to A =1500ps
latency from clk to B =200ps

clk period =1000ps

In this case to balance skew, should the latency of B be increased by 300 or 1300?

Diagram given in this link:

https://obrazki.elektroda.pl/95_1319485590.png

 

[huckle]

let's assume A is talking to B

latency from clk to A =1500ps
latency from clk to B =200ps

clk period =1000ps

In this case to balance skew, should the latency of B be increased by 300 or 1300?

Diagram given in this link:

https://obrazki.elektroda.pl/95_1319485590.png

Since they both get the same clock, Assuming the max_skew allowed is 0ps, latency of B should be increased by 1300ps (to make it 1500ps also).

 

[pradeeppiskala]

https://obrazki.elektroda.pl/33_1319507133.png

1300ps means more buffers and would increase power consumption.

if we increase delay of clk path to B by 300ps, the launch edge for both flops A and B would happen at the same instant. we can get the output at B after one cycle.

is this correct?

 

[lostinxlation]

why do you want to increase by 300 ? you said 'in case to balance....", it means you want to target 1500ps latency or whatever that makes the same insertion delay to all the flops.

 

[pradeeppiskala]

balance as in the launch edge for both flops would be at the same instant.

increasing the insertion delay by 300 would give the same output(at register B) as increasing the delay by 1300. correct me if a wrong?

 

[huckle]

balance as in the launch edge for both flops would be at the same instant.

increasing the insertion delay by 300 would give the same output(at register B) as increasing the delay by 1300. correct me if a wrong?

Are you adding the clock period in your calculation? The clock period is independent of the delay that needs to be added. 1500ps - 200ps = 1300ps needs to be added.

Regards,

 

[albbg]

I think you can add just 300 ps. I
You will have the rising (for instance) edge on A delayed by 1.5 cycles and on B delayed 0.5 cycles then both of them will see a rising edge at the same time even if the two edges are coming from different cycles of the original clock waveform. However, in this case, you will have to take into account the cycle-by-cycle jitter that will be added and will generate additional skew between A and B.

 

[oratie]

This is incorrect, the static timing analysis tool (DC or ptime or ...) will show you, that clock on B comes 1 period earlier than on A, so the slack will be always negative. The only correct decision is to have the both clock latency equal to 1500ps.

 

[pradeeppiskala]

Are you adding the clock period in your calculation? The clock period is independent of the delay that needs to be added. 1500ps - 200ps = 1300ps needs to be added.

Regards,

Yes I am using clock period for delay calculation. will the circuit not behave correctly when the insertion delay to b is increased by 300?

---------- Post added at 09:15 ---------- Previous post was at 09:13 ----------

I think you can add just 300 ps. I
You will have the rising (for instance) edge on A delayed by 1.5 cycles and on B delayed 0.5 cycles then both of them will see a rising edge at the same time even if the two edges are coming from different cycles of the original clock waveform. However, in this case, you will have to take into account the cycle-by-cycle jitter that will be added and will generate additional skew between A and B.

I agree with you

 

[oratie]

Let's consider such circuit: Input_port -> A_reg -> (logic) -> B_reg -> Output_port.

We assumed, that data from Input_port will be observed on Output_port after two clock cycles (because only two registers on the path between Input and Output. In your case, the data required three clock cycles.

First cycle the B_reg will capture unknown data from A_reg, because the A_reg is still waiting for the clock edge. During the second cycle, A_reg will capture data from the input_port, and during the third cycle, B_reg will capture the data and pass it it to the Output_port.

 

[pradeeppiskala]

Let's consider such circuit: Input_port -> A_reg -> (logic) -> B_reg -> Output_port.

We assumed, that data from Input_port will be observed on Output_port after two clock cycles (because only two registers on the path between Input and Output. In your case, the data required three clock cycles.

First cycle the B_reg will capture unknown data from A_reg, because the A_reg is still waiting for the clock edge. During the second cycle, A_reg will capture data from the input_port, and during the third cycle, B_reg will capture the data and pass it it to the Output_port.

Ture, that is only when we start the clock for the first time, it takes 3 cycles. once the clock is running, the data from input to output will come after 2 cycles.

Even if the insertion delay is made equal 1500ps for both paths, it will take 3 cycle for the first correct data to come out. once the clock is running, it will take 2 cycles from input to output.

 

[oratie]

OK, let's look from another side: The new data came on Input_port each clock cycle. The first data (accompanied by first clock cycle) will be lost, because A_reg will capture nothing during first cycle, and during the second cycle the first data will be overwritten by the second data (accompanied by the second clock cycle).

 

[pradeeppiskala]

The diagram is relating the clock delay. not the time taken for input to reach the data pin. A_reg will capture data as soon as the input is given at the data pin.


input_clock_port > a_reg_clk_pin
input_clock_port > b_reg_clk_pin

No data path delay

 

[lostinxlation]

Ture, that is only when we start the clock for the first time, it takes 3 cycles. once the clock is running, the data from input to output will come after 2 cycles..

You need to understand how the tool works. As having been said, the tool knows which edge and which edge are related for setup and hold, and just skewing the clock by 1 cycle would cause a lot of violation in timing analysis.. Also when you run test pattern generation or logic verification with sdf, it will grossly fail too.

 

[lostinxlation]

And if you have clock gatings in a certain way, your logic doesn't function correctly either. Unless you have a very good understanding in chip design including logic design and design flow, trying this kind of trick will lead to a disaster.

 

[pradeeppiskala]

You need to understand how the tool works. As having been said, the tool knows which edge and which edge are related for setup and hold, and just skewing the clock by 1 cycle would cause a lot of violation in timing analysis.. Also when you run test pattern generation or logic verification with sdf, it will grossly fail too.

I agree, the tool would give violations. Is it problem with tool ?

will adding 300ps to clock path of B result in wrong data being latched at the ouput of B?

 

[dftrtl]

First of all for a clock period of 1000 ps having skew of 1500 ps is rubbish. If you have this kind of design REG A cannot capture right data.
Let me know if you have any doubts.