let's assume A is talking to B
latency from clk to A =1500ps
latency from clk to B =200ps
clk period =1000ps
In this case to balance skew, should the latency of B be increased by 300 or 1300?
Diagram given in this link:
https://obrazki.elektroda.pl/95_1319485590.png
balance as in the launch edge for both flops would be at the same instant.
increasing the insertion delay by 300 would give the same output(at register B) as increasing the delay by 1300. correct me if a wrong?
Are you adding the clock period in your calculation? The clock period is independent of the delay that needs to be added. 1500ps - 200ps = 1300ps needs to be added.
Regards,
I think you can add just 300 ps. I
You will have the rising (for instance) edge on A delayed by 1.5 cycles and on B delayed 0.5 cycles then both of them will see a rising edge at the same time even if the two edges are coming from different cycles of the original clock waveform. However, in this case, you will have to take into account the cycle-by-cycle jitter that will be added and will generate additional skew between A and B.
Let's consider such circuit: Input_port -> A_reg -> (logic) -> B_reg -> Output_port.
We assumed, that data from Input_port will be observed on Output_port after two clock cycles (because only two registers on the path between Input and Output. In your case, the data required three clock cycles.
First cycle the B_reg will capture unknown data from A_reg, because the A_reg is still waiting for the clock edge. During the second cycle, A_reg will capture data from the input_port, and during the third cycle, B_reg will capture the data and pass it it to the Output_port.
You need to understand how the tool works. As having been said, the tool knows which edge and which edge are related for setup and hold, and just skewing the clock by 1 cycle would cause a lot of violation in timing analysis.. Also when you run test pattern generation or logic verification with sdf, it will grossly fail too.Ture, that is only when we start the clock for the first time, it takes 3 cycles. once the clock is running, the data from input to output will come after 2 cycles..
You need to understand how the tool works. As having been said, the tool knows which edge and which edge are related for setup and hold, and just skewing the clock by 1 cycle would cause a lot of violation in timing analysis.. Also when you run test pattern generation or logic verification with sdf, it will grossly fail too.
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