One way to "direct" the synthesis tool for gated clock is to put enable signal on every sequential logic.
Like:
Flip-flops with an asynchronous reset and synchronous enable (good strategy for low power)
PHP:
always_ff @(posedge clk or negedge rstb)
if ( rstb != 1'b1) begin
... // Asynchronous set/reset actions
end
else begin
if (enable_condition==1'b1 ) begin
... // Synchronous actions
end