mordak
Member level 5
- Joined
- Mar 8, 2013
- Messages
- 82
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Location
- Neverland
- Activity points
- 2,134
Hello,
In a current steering DAC I designed there are glitches due to the switching transistors. I use some DACs in my delta sigma ADC, the current of the first DAC varies slightly due to the glitches, i.e if it's supposed to be 8.5uA, it would be 8.7uA right after the switching and the it settles to the steady state, which is 8.5uA. I used low-swing, high-crossing switch drivers for controlling DAC switches, to decrease the glitche, which actually helped a lot. But my last DAC, which provides a few hundred nano amps would be significantly affected by those glitches, i.e if the current is supposed to be 100nA, it reaches to 400nA at the switching time and then reaches to 100nA. The switching circuit I used for the last DAC is just the one I used for the first DAC, but since current is less, that glitch screws the current. Since the last DAC in delta sigma ADC is not as important as the first one, I thought those glitches may not be big deal, but now I get a warning from simulation software that transistors used in a stage after that last DAC would be melted due to exceeding Imelt. I appreciate if someone help me with this problem.
Tnx
In a current steering DAC I designed there are glitches due to the switching transistors. I use some DACs in my delta sigma ADC, the current of the first DAC varies slightly due to the glitches, i.e if it's supposed to be 8.5uA, it would be 8.7uA right after the switching and the it settles to the steady state, which is 8.5uA. I used low-swing, high-crossing switch drivers for controlling DAC switches, to decrease the glitche, which actually helped a lot. But my last DAC, which provides a few hundred nano amps would be significantly affected by those glitches, i.e if the current is supposed to be 100nA, it reaches to 400nA at the switching time and then reaches to 100nA. The switching circuit I used for the last DAC is just the one I used for the first DAC, but since current is less, that glitch screws the current. Since the last DAC in delta sigma ADC is not as important as the first one, I thought those glitches may not be big deal, but now I get a warning from simulation software that transistors used in a stage after that last DAC would be melted due to exceeding Imelt. I appreciate if someone help me with this problem.
Tnx