Glitch power during gate-level simulations

[heerasignh]

Hi. This is my first post on EDA forum. I am currently doing unit delay gate-level simulations. I see lot of glitch power in my design. In order to trace the glitch, I would like to count the number of gates through which the glitch propagates until it hits a sequential and stops. Is there a way to get this count during vcs simulation or I can see how the activity is being propagated?

 

[ljcox]

You should do the design so it does not generate glitches.

I can't comment further without seeing your circuit.