Hi,
I sometimes use an up-down-counter as filter.
Clk = system_clock
EN = either 1 or a divided system clock
Dir = is the input I want to de-glitch
Thus a "1" signal makes the counter to count up
a "0" signal makes the counter to count down.
On upper limit I set the the (deglitched) output as "1", and prevent the counter from further counting up
On lower limit I set the the (deglitched) output as "0", and prevent the counter from further counting down
on a 4 bit counter you could set the lower limit to "0" and the upper limit to "15" (decimal)
Then you get a deglitch time of 15 counter_clock_cycles in both directions.
In case of a n "wrong" glitches you need 2 x n extra counts for the output to switch.
This saves flipflops especially for long deglitch times.
With n flipflops you can get a delay time of up to 2^(n-1) -1 clock cycles... in both directions.
Klaus