Getting the most capacitor size per area

[alex2013]

Hi,
Anyone can give me ideas on how to get the most capacitance size per silicon area?
It is for charge storage capacitor, so one end will be connected to ground, and the other end to charging input/output.
What I can think about is "Use MIM stacked above MOSVAR".
Will there be any foreseeable problem with this?
I am torn between using small unit capacitance (can get more cap size from fringe capacitance, but inter-unit-cap layout limitation will reduce area actually covered by capacitors) and large unit capacitance (the other way around).

Any other ideas?
Any other cap type can we stack between MOSVAR and MIM? (well maybe MOM, but my foundry unlikely have the model for that).

Thanks

 

[erikl]

What I can think about is "Use MIM stacked above MOSVAR". Will there be any foreseeable problem with this?

That's fine, if your foundry's Design Rules allow for.

I am torn between using small unit capacitance (can get more cap size from fringe capacitance, but inter-unit-cap layout limitation will reduce area actually covered by capacitors) and large unit capacitance (the other way around).

If you don't mind about accurate cap modeling (and you probably don't in case of a storage cap), you can use large caps. But mind their ESR: use enough contacts for metalization.

Any other cap type can we stack between MOSVAR and MIM? (well maybe MOM, but my foundry unlikely have the model for that).

Good idea but no parsnips. Anyway you'd need some metal layers for underneath routing.