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Get Error: (vsim-3033)as I am trying to do RTL-timing simulation using Modelsim

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hello everyone
please , kindly help me
I finished writing my design using verilog, functional simulation by modelsim is working well. then I synthesized my design by using ( Encounter(R) RTL Compiler RC10.1.306 ) to create the netlist and SDF (standard delay format) files successfully . I used TSMC 0.18μm CMOS process timing library.
I am trying to make timing simulation for netlist design by modelsim using same testbench file I used for functional simulation before .
but unfortunately I get many errors as this;
Error: (vsim-3033) <project file path>(278690): Instantiation of 'BUFTD1BWP7T' failed. The design unit was not found.
this error because this cells 'BUFTD1BWP7T' in the netlist file which has been added from the technology library and it is defined in the library file.
how I can include the timing library in my project in modelsim to overcome this error . or anyone have the functional modules of the standard cells in verilog or VHDL so
I can include it in my design.
please help me to solve this problem , I don't have enough time ! it is my graduation project and I must finish the timing simulation . thanks in advance

this photo for the instantiated cells in my Netlist file
1614980586513.png


and this photo for the cells definition in the timing library

1614980623178.png
 

ThisIsNotSam

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every standard cell library comes with a verilog file that is for this type of gate level simulation. look for it in your installation folder or ask your colleagues.
 
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thank you for your reply , I will ask my colleagues about it , however in case there are no verilog modules available for the standard cells then how can I get it ? is there any other option?
thank you soo much
 
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every standard cell library comes with a verilog file that is for this type of gate level simulation. look for it in your installation folder or ask your colleagues.
hello dear
I couldn't find the verilog module files in installation folder , what should i do ?
please help me
 

ThisIsNotSam

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look harder or accept that your installation is incomplete?! It's pretty weird to ask for help to locate a file...
 

dpaul

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I couldn't find the verilog module files in installation folder , what should i do ?
It is a standard cell library and not a user defined logic block. May be they are there inside a completely separate directory and not within the dirs where you are generally keeping the Verilog design files. As !sam said, ask a senior colleague of yours.
 

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