atieh
Newbie level 3

hi dears,
I am working on a project to compare standard inverter and MRF inverter. MRF inverter is a model of inverter which is so resistive to noise. so, I need to generate external noise to both standard inverter and MRF inverter circuits (in cadence software) to show that the standart inverter output (waveform) will be noisy where as the MRF circuit output is the same as befire (means that resistive to noise).
I designed both circuits without noise, and I could get the correct waveforms. now, my problem is that I dont know how to generate external noise. I did some research and I ve seen that there are three ways to do. first using 'vpwlfile', by generating noise in matlab and open it here. second to use verilog-A. and third is to use vsource.
now, the problem is that I dont know how to do any one of them. can you plz help me and explain to me how to generate noise for example using vpwlf?.
I appreciate your consideration
rgds
Atieh
I am working on a project to compare standard inverter and MRF inverter. MRF inverter is a model of inverter which is so resistive to noise. so, I need to generate external noise to both standard inverter and MRF inverter circuits (in cadence software) to show that the standart inverter output (waveform) will be noisy where as the MRF circuit output is the same as befire (means that resistive to noise).
I designed both circuits without noise, and I could get the correct waveforms. now, my problem is that I dont know how to generate external noise. I did some research and I ve seen that there are three ways to do. first using 'vpwlfile', by generating noise in matlab and open it here. second to use verilog-A. and third is to use vsource.
now, the problem is that I dont know how to do any one of them. can you plz help me and explain to me how to generate noise for example using vpwlf?.
I appreciate your consideration
rgds
Atieh