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Generating Verilog Timing Libraries for Gates

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dhaval4987

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Dear All,

I need to generate test patterns for same circuit in different operation condition. I checked Tetramax- and found out that it takes Timing libraries only in Verilog format.

I have just one timing library in verilog. How do I generate one library for different different operating conditions?

Thanks and Regards,

Dhaval.
 

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