futuredreamer
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Hello,
I've designed a circuit consists of multiple modules and the top level is just instantiation from these modules. I've imported the netlist to Design Architect and generated the schematic but the issue appeared when I'm trying to prepare the layout all these instantiations is just empty blocks and don't contain any logic, how can I solve this?
Thanks in advance
I've designed a circuit consists of multiple modules and the top level is just instantiation from these modules. I've imported the netlist to Design Architect and generated the schematic but the issue appeared when I'm trying to prepare the layout all these instantiations is just empty blocks and don't contain any logic, how can I solve this?
Thanks in advance
