Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

generating clk signal

Status
Not open for further replies.

sameena

Newbie level 1
Joined
Mar 25, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,285
sir,
iam generating 100mhz signal in xilinx in verilog using dcm ,,,,plz help me in writing code
 

Sure. Download the datasheet for the fpga you are using. Specifically read the chapter on "clocking resources". That gives you plenty of information, and will get you well underway to including a DCM in your design. Good luck!

PS: if that is too much work for you, then fire up coregen from ISE and click through the clocking wizard.

PPS: if that is too much work, google for some source code.

PPPS: if that is too much work, pursue a career in management or something.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top