Generating BRAM with core Generator

[lahrach]

Hi friends,

why the wea signal is written as

wea : in STD_LOGIC_VECTOR(0 downto 0);

How to instantiat it?

thanks,

 

[barry]

I've run into this quirk before, and don't really understand it. The only solution that I'm aware of is to declare the signal driving that input the same way, i.e., std_logic_vector(0 downto 0).

There shouldn't be any problem instantiating it, just follow the convention.

 

[ads_ee]

It's not a quirk. It's a result of the underlying scripts that produce the core generating code for signals/ports that can be 1 to n bits wide.

I suppose it could be considered a bug in the script, but I think it was intentional to make it easier to generate the code without resorting to a bunch of if's for every parameterizable bus width.

 

[barry]

Multiple write enables? I find that hard to believe.

 

[ads_ee]

Like I said it could be considered a bug in the script...

I've seen this kind of port generation in both Xilinx and Altera produce code. I really believe it just a way for them to simplify the script so it can generate various widths for signals. Like the byte write enables, that change width depending on the data width of the ram.

I've seen it recently on a MIG core that has output wire [BW_WIDTH-1:0] bw_n;, where BW_WIDTH is 1

If the script writer is sloppy then I can easily believe it was done on the wea too.

 

[barry]

I think it's sloppy work. The tool shouldn't present the user with some 'abnormal' output just to ease the script writer's job. To add a bunch of if statements in order to generate proper output would seem to be the right way to go. It's not as if the tool would run noticeably slower.

 

[ads_ee]

don't complain about it to me, I've been telling the same thing to the FAEs for both Xilinx and Altera. You see how much good that's done. ;-)

 

[barry]

I don't even talk to Altera anymore. (Mainly, because they would never talk to me.) I use Xilinx or Lattice, not Altera.:-x

 

[BlackHelicopter]

It's a one-element vector. I've seen this used before, although it's not very common.
1. Could be used for future expansion
2. If I/O nets are defined in a constraint file as an vector and only one element is needed, that's how it would be written.
For instance:
NET "WEA<2>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "WEA<1>" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "WEA<0>" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;