Generating a Verilog Netlist

[dhaval4987]

How do I convert the schematic into a verilog netlist that could be used in another tool?

 

[iwpia50s]

This question is a little too generic. What is your source? How was the schematic generated? Does the tool you used to generate the schematic have the option to export Verilog?

 

[dhaval4987]

This question is a little too generic. What is your source? How was the schematic generated? Does the tool you used to generate the schematic have the option to export Verilog?

Thanks iwpia50s;

Say I will be using Cadence Schematic Editor for making a circuit.

How do I get a verilog netlist in that case?

 

[iwpia50s]

Is this a SPICE circuit or, are you connecting gate in a schematic capture tool? I believe the tool should be able to export Verilog if you are connecting gates in the schematic capture tool.

 

[dhaval4987]

Is this a SPICE circuit or, are you connecting gate in a schematic capture tool? I believe the tool should be able to export Verilog if you are connecting gates in the schematic capture tool.

Well, It is just a schematic editor, but I am using Spectre mode for analysis. It generates the netlist but it is not in *.v format.

 

[iwpia50s]

So I'm still not sure how you got the design into the schematic tool. Did you instantiate gates or transistors? If you instantiated gates then the tool should export gates in verilog. If you instantiated transistors then I'm not sure what you should do.

 

[dhaval4987]

So I'm still not sure how you got the design into the schematic tool. Did you instantiate gates or transistors? If you instantiated gates then the tool should export gates in verilog. If you instantiated transistors then I'm not sure what you should do.

I am using readily available gates. So yes, I am instantiating the gates. But I dont see any option anywhere that allows me to export verilog.

 

[Chethan]

Hi,
You cannot get a verilog file from a schematic. No tools are soo intelligent. You can get a schematic netlist from a schmatic. That is a transistor/gate level description of your circuit.
regards
Chethan

 

[dhaval4987]

Okay,

How about the other way around? Say from verilog to schematic?

 

[Chethan]

Hi,
If your verilog code is a small one, then you can handwrite the schematic by reading the verilog file. But again there are no tools which can convert your verilog code to schematic.

 

[dhaval4987]

Hmm... The thing is that I want to do generic timing analysis for circuits. It should be generic and I want to compare the results which I obtained via hand calculations and the results obtained by simulating verilog.

I have obtained some verilog descriptions of some ISCAS benchmark circuits. Just dont know how to verify whether I am going on a correct path or not!

 

[Chethan]

If you want to do a generic timing analysis using some bench mark circuits then u can build a verilog test bench and simulate them. create a test bench using any standard verilog tools like ncverilog or verilogxl and simulate ur design.

 

[ljxpjpjljx]

why you want to do so ?