Generating a clean, synchronous reset from noisy asynchronous inputs

[waljit]

Hi all,

I am just coding up (VHDL) a design and am pondering the best strategy for creating a clean, synchronous reset signal from noisy asynchronous reset inputs.

My circuit is this: I have an FPGA, with its own dedicated clock input (on a global clock pin) from a local oscillator. The FPGA has 2 reset inputs; one comes from a power-on-reset IC (voltage detector) which is monitoring the 3.3V supply - I expect this should be pretty clean. The other reset input is from a reset pushbutton, which definitely will not be clean!

I want my logic to provide a clean, debounced reset to the reset of the system, which is asserted asynchronously but de-asserted synchronously (i.e. a reset synchronizer).

Before I code it up, I thought I'd draw the circuit to check I am happy with it. The attached is what I came up with. Does it look like a sensible scheme to you?



From left to right:

The first 2 flops synchronise the 2 reset inputs to the local clock domain.
This then feeds a debouncer, which consists of 3 further flops and a counter.
Finally, there is a reset synchroniser.

Any comments most welcome!

thanks
Waljit

 

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Looks fine to me, in fact it looks pretty much identical to the circuit I normally use. Though I have separate "library" modules for each of the three blocks. Makes it easy to find synchronizer registers in a netlist when they all have SYNC_REG or something like that in their name

I think this is the first time I've seen someone post a schematic of their circuit design before posting their HDL code. I applaud you, this is the way you should design things. Now describing it in HDL should be easy. Even if you start with HDL directly you should already have a vision of what the circuit looks like in your head.

 

[TrickyDicky]

To the OP - you can also use a shift register where the input is constant '0'. The shift register is async reset by your synchronised reset. Then you get a nice long reset pulse.

I think this is the first time I've seen someone post a schematic of their circuit design before posting their HDL code. I applaud you, this is the way you should design things. Now describing it in HDL should be easy. Even if you start with HDL directly you should already have a vision of what the circuit looks like in your head.

I assume there wont be any HDL, as this is the Quartus schematic editor.

 

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I assume there wont be any HDL, as this is the Quartus schematic editor.

Now I'm completely disappointed...

OP, In my opinion using the schematic editor in an FPGA tool chain is just a sneaky way the vendor uses to lock you into their parts. I avoid using those tools primarily because of that. I'd rather have the option of saying "Altera you're prices are too high, we can get part XYZ and it meets our requirements for a lot cheaper, so stick it!". When that happens (many times it's not me but management/purchasing) and I'm told to switch to a different part to reduce cost I like the fact that I can quickly change out the instantiated memory (if I have any), create a new pinout, new constraint file, and implement the design. Of course the board designer is going to be over the change for the next month, but I'm done in 1-2 days .

 

[waljit]

Hi all,

Thanks for the quick replies.

I agree about schematics. Rest assured, this will be in VHDL. I only used Quartus schematics as it was the quickest way of getting a picture of a circuit diagram to post on here.

Waljit

 

[std_match]

I think an inverter is needed before the "cnt_en" input on the counter.
As it is now, the counter will disable itself when it is resetted.