generating a 1 clk cycle pulse

[nesta]

Hi VhdlExperts,

i have a requirement in which i need to generate a ready pulse for 1 clk cycle on some condition.

However i am not finding a way to do it with a process having sensitivity list in it.


The scenario is the rdy signal will be set high by a different process and it should be only 1 clock cycle only.

--- Code snippet for explanation ----

entity gate is
port(rdy : IN std_logic;
-----
);
end entity;

architecture beh of gate is

signal rdy_con : std_logic;

begin

rdy_con <= rdy;

process(clk,rdy)
begin
if(clk ='1' and clk'event) then
if(rdy = '1') then
--- do some processing;
rdy <= '0'; --- this does not toggle to zero(why)

end if;
end if;
end process;
end arch;

------------------------------

Thanks in advance,
Nesta

 

[j_andr]

latch your <ready_conditions> in a flip-flop,
say ready_reg;
then assign the ready signal as:
<ready_conditions> TRUE and ready_reg FALSE;
this should generate one clock cycle pulse
---
J.A

 

[alexan_e]

The code you have presented can't work, rdy is an input and you are trying to assign a value to it.

Alex

 

[nesta]

Sorry for the mistake, the actual code is (rdy_con )which is connected to the input rdy,,
It was just a barebone to explain my intentions.

rdy_con <= '0'; --- this does not toggle to zero(why)


J_andr thanks for your suggestion , will try out.

 

[nesta]

latch your <ready_conditions> in a flip-flop,
say ready_reg;
then assign the ready signal as:
<ready_conditions> TRUE and ready_reg FALSE;
this should generate one clock cycle pulse
---
J.A

Sorry couldn't quite understand how to assign the ready signal .. cud plz elaborate with some simple pseudocode.

 

[FvM]

Your question isn't complete. We have to know:
- is the input rdy synchrounous to clk? You forgot to add clk to the entity port, by the way.
- how long rdy will be active? Longer than one clock cycle, possibly even shorter?

A typical case would be rdy unrelated to clk and active at least one clk cycle. Then rdy must be syncronized to the clk domain and edge detection has to be performed. It's usually done by shifting the input signal into a register chain.

process (clk)
begin
  if rising_edge(clk) then
    rdy_reg(2 downto 0) <= rdy_reg(1 downto 0) & rdy
    if rdy_reg(2 downto 1) = "01" then -- positive edge detected
    --- do some processing;
    end if;
  end if;
end process;

Unfortunately, the synchronous processing is involving a delay.

 

[j_andr]

a simple example in verilog, hope you will not have a problem to translate
it to vhdl

/.../
input  rdy;

reg   rdy_reg;         // flip-flop to store rdy value

always @(posedge clk)
  rdy_reg <= rdy;       // clocked process in vhdl

wire ready = (rdy && !rdy_reg); // rdy HIGH and rdy_reg LOW
                              // one cycle pulse when rdy changes from 'L' to 'H'

 if ( ready == 1'b1 )
   < do some processing >

---
J.A

 

[nesta]

Sorry for not being very clear, basically i am using this ready signal (as an asynchronous input) for some kind of data pattern assertion.
I would like to assert the ready signal (~1clk cycle) only whenever there is some known data pattern; rest of the time it should be deasserted.

data = ____(-----)(invalid data)_(invalid data)~___(xxxx)____(-----)_____

ready = ____|--|____________~__________________________|--|______

My problem is i know how to make ready go high but am unable to pull it low which causes ready to be high forever.

ready = _____|--------------------------------------- ( high always)

This is my main issue.

 

[alexan_e]

I think you can use "flancter"

An example of the method if this

---

Code VHDL - [expand]
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------------------------------------------------------------------ -----
-- FileName: flancter.vhd
-- Author: Rob Weinstein
-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity flancter is
port (  ASYNC_RESET:in   std_logic;
        SET_CLK    :in   std_logic;
        SET_CE     :in   std_logic;
        RESET_CLK  :in   std_logic;
        RESET_CE   :in   std_logic;
        FLAG_OUT   :out  std_logic);
end flancter;  
 
architecture flancter of flancter is
 signal SetFlop: std_logic;
 signal RstFlop: std_logic;
 
 begin
 
 --The Set flip-flop
 set_proc:process(ASYNC_RESET, SET_CLK)
 begin
    if ASYNC_RESET = '1' then
        SetFlop <= '0';
    elsif rising_edge(SET_CLK) then
        if SET_CE = '1' then
            -- Flops get opposite logic levels.
            SetFlop <= not RstFlop;
        end if;
    end if;
    
end process;
 
 --The Reset flip-flop
 reset_proc:process(ASYNC_RESET, RESET_CLK)
 begin
    if ASYNC_RESET = '1' then
        RstFlop <= '0';
    elsif rising_edge(RESET_CLK) then
        if RESET_CE = '1' then
            -- Flops get the same logic levels.
            RstFlop <= SetFlop;
            end if;
        end if;
    end process;
 
FLAG_OUT <= SetFlop xor RstFlop;
 
end flancter;

---

"How to set a status flag in one clock domain, clear it in another, and never, ever have to use an asynchronous clear for anything but reset"

https://www.floobydust.com/flancter/Flancter_App_Note.pdf

Alex

 

[j_andr]

Sorry for not being very /.../

data = ____(-----)(invalid data)_(invalid data)~___(xxxx)____(-----)_____

ready = ____|--|____________~__________________________|--|______

My problem is i know how to make ready go high but am unable to pull it low which causes ready to be high forever.

ready = _____|--------------------------------------- ( high always)

This is my main issue.

I try to guess what you need, possible I guess wrong
but may be this example helps ?

always @(posedge clk)
if ( ready == 1'b1 ) ready <= 1'b0; // if ready set clear it on next clock slope;
else if ( data == pattern ) ready <= 1'b1; // set ready if data match pattern
---
J.A

 

[FvM]

I try to guess what you need, possible I guess wrong
but may be this example helps ?

Looks like you are exactly copying the non-working code from the original post.

just make these changes in your code

The only suggested "change" is an empty asynchronous reset condition. Do you really mean, that it will change anything? It doesn't. All errors in the original code are kept.

 

[jimmy_tag]

Looks like you are exactly copying the non-working code from the original post.

The only suggested "change" is an empty asynchronous reset condition. Do you really mean, that it will change anything? It doesn't. All errors in the original code are kept.

you better compile it yourself first then talk. And yes, till now my codes are working perfectly using this condition. And Who said its a Asynchronous Reset, did I mentioned that?? I just initialized signal with name 'rst', it dosent mean its a reset signal.

You should read the complete code first.

And about the

I try to guess what you need, possible I guess wrong
but may be this example helps ?

just make these changes

You should explain an english boy in english rather than in japanese. So I explained the code in VHDL. No offence to j_andr

 

[alexan_e]

you better compile it yourself first then talk. And yes, till now my codes are working perfectly using this condition. And Who said its a Asynchronous Reset, did I mentioned that?? I just initialized signal with name 'rst', it dosent mean its a reset signal.

---

Code VHDL - [expand]
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if rst='1' then
(dont write anything here)
elsif (clk ='1' and clk'event) then
if (rdy = '1') then
--- do some processing;
rdy <= '0';

---

It looks like a typical asynchronous reset code, you just haven't written any code in it.

You should read the complete code first.

How do you expect it to work when you assign a value to the input rdy <= '0';

Alex

 

[jimmy_tag]

---

Code VHDL - [expand]
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if rst='1' then
(dont write anything here)
elsif (clk ='1' and clk'event) then
if (rdy = '1') then
--- do some processing;
rdy <= '0';

---

It looks like a typical asynchronous reset code, you just haven't written any code in it.



How do you expect it to work when you assign a value to the input rdy <= '0';

Alex

My apologises to FvM. I think i was too exited. I shouldnt have done that. I made corrections now.

---------- Post added at 20:18 ---------- Previous post was at 20:09 ----------

I think the main question actually is incomplete.