Generating 20M Clock from 50M

[aafaq]

can any one generate 20M clock from 50 M. But it should be with sharp edges without any gittering i need very accurate one (using spartan 3e1600 )
with very accurate i mean that i need sharp edges and fifty percent duty cycle
and Zerox 100 plz upload the code now if possible

 

[kvingle]

Re: 20M Clock from 50M

You didn't comment on hardware you are using...well if it is a xillinx
device with DCM available in it....go for DCM.Use CLKDV port
and divide by value as 2.5 .....
If you don't know how to use DCM refer to
spartan libraries in your xilinx docs folder...
regards..

 

[Zerox100]

Re: 20M Clock from 50M

Ok kvingle is right but if you aren't using Xilinx you can use a divider by 2.5. I have its code. If you need it let me know.

 

[echo47]

20M Clock from 50M

Hi aafaq, Your words "very accurate" are vague. Can you clarify your requirement?

Gittering? Do you mean jitter? It is impossible to completely eliminate jitter.

 

[Zerox100]

Re: 20M Clock from 50M

this the code:

library IEEE;
use ieee.std_logic_1164.all;

entity divide2_5 is
port (
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);
end divide2_5;

architecture st of divide2_5 is
signal d, q, p : std_logic_vector (1 downto 0);
signal fb : std_logic;

begin

process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= p(0);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
p(0) <= '0';
elsif (clk'event and clk = '1') then
p(0) <= d(0);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= p(1);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
p(1) <= '0';
elsif (clk'event and clk = '0') then
p(1) <= d(1);
end if;
end process;

fb <= NOT(q(0) OR q(1) or p(1) OR P(0));
d(0)<= fb;
d(1)<= fb;
--div <= fb; --20%
div <= p(0) or p(1); --40%

end st;



if it is usefull please press it helped me!