Re: 20M Clock from 50M
this the code:
library IEEE;
use ieee.std_logic_1164.all;
entity divide2_5 is
port (
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);
end divide2_5;
architecture st of divide2_5 is
signal d, q, p : std_logic_vector (1 downto 0);
signal fb : std_logic;
begin
process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= p(0);
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
p(0) <= '0';
elsif (clk'event and clk = '1') then
p(0) <= d(0);
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= p(1);
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
p(1) <= '0';
elsif (clk'event and clk = '0') then
p(1) <= d(1);
end if;
end process;
fb <= NOT(q(0) OR q(1) or p(1) OR P(0));
d(0)<= fb;
d(1)<= fb;
--div <= fb; --20%
div <= p(0) or p(1); --40%
end st;
if it is usefull please press it helped me!