generate twice the frequency of pulse from clock source

[jmlabuac]

please help me... I'm using verilog... I'll be having an input clock of say 1Mhz.. I need to produce a signal twice as fast as the input clock... please help

 

[mister_rf]

https://www.edaboard.com/threads/91315/

 

[jmlabuac]

I need a verilog code for it... I don't know how to translate the given circuit to verilog...

 

[ravics]

If you're using a Xilinx FPGA you may use a DCM primitive with Digital Frequency Synthesis option to generate multiples. Even Clk_2X is supported in DCM.

 

[imbichie]

Hi,

For doubling the frequency you should use the PLL in your FPGA for better result

 

[xtcx]

please help me... I'm using verilog... I'll be having an input clock of say 1Mhz.. I need to produce a signal twice as fast as the input clock... please help

It depends on which vendor device you are using to. For xilinx you can use DCM from Logicore IP wizard and similarly for Altera you can use PLL megawizard to implement the clock multiplier.