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generate test pattern of delay path fault

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coolwall

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Dear All,
I have a question on delay path fault test pattern generation. As we know, to test the delay path fault we need two test vector, v1 and v2. V1 is to initialize the circuit, and V2 applies to the circuit to generate a transition on the path under testing. Given a path under testing, is there a way I can get v1 and v2?

This is what I have done. I use ISCAS85 as benchmark. Synthesize and insert scan cell on it, and get several long paths using PrimeTime. Given these paths, in Tetramax, I can generate test pattern in stil or wgl format. But I think these two formats are too difficult to get v1 and v2.

Looking forward for your advise. Thank you in advance.
 

Tetramax always generate the STIL of WGL file format file.SO If u want the v1 and v2, u have to go through the STIL file.
 

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